R.P. Agarwal

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent @p-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.

An analytical approach to dynamic crosstalk in coupled interconnects

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.

Repeater insertion in global interconnects in VLSI circuits

Purpose – Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.Design/methodology/approach – Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.Findings – Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new fi...

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects

Purpose – To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.Design/methodology/approach – Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size Wn=3.9 μm and Wp=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. VA sw...

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ~78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a +/-10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (~40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.

Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects

– This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects., – The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width., – It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver., – While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Crosstalk analysis of simultaneously switching interconnects

This article focusses on the waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A low loss coupled transmission line-model of interconnect is used for analytical purpose. Noise peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analysed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modelled as linear resistance. Comparison of the analytical results with simulation programme with integrated circuit emphasis (SPICE)-extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of-phase switching, respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks, their timings and waveform shape for all switching conditions with an average error of less than 4%.

An analysis of interconnect delay minimization by low-voltage repeater insertion

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.

Width optimization of global inductive VLSI interconnects

Purpose – The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.Design/methodology/approach – Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.Findings – For a d...