Ro-Min Weng

Error concealment of lost motion vectors with overlapped motion compensation

Most video sequence coding systems use block motion compensation to remove temporal redundancy for video compression due to the regularity and simplicity. A new error concealment algorithm for recovering the lost or erroneously received motion vectors is presented. It combines the overlapped motion compensation and the side match criterion to make the effect of lost motion vectors subjectively imperceptible. The side match criterion takes advantage of the spatial contiguity and interpixel correlation of image to select the best-fit replacement among the motion vectors of spatially contiguous candidate blocks. Particularly, to mask the blocking artifacts, we incorporate an overlapping technique to create a subjectively closer approximation to the true error-free image.

A Low-Power Full-Band Low-Noise Amplifier for Ultra-Wideband Receivers

In this paper, a low-power full-band low-noise amplifier (FB-LNA) for ultra-wideband applications is presented. The proposed FB-LNA uses a stagger-tuning technique to extend the full bandwidth from 3.1 to 10.6 GHz. A current-reused architecture is employed to decrease the power consumption. By using an input common-gate stage, the input resistance of 50 Ω can be obtained without an extra input-matching network. The output matching is achieved by cascading an output common-drain stage. FB-LNA was implemented with a TSMC 0.18-μm CMOS process. On-wafer measurement shows an average power gain of 9.7 dB within the full operation band. The input reflection coefficient and the output reflection coefficient are both less than -10 dB over the entire band. The noise figure of the full band remained under 7 dB with a minimum value of 5.27 dB. The linearity of input third-order intercept point is -2.23 dBm. The power consumptions at 1.5-V supply voltage without an output buffer is 4.5 mW. The chip area occupies 1.17 × 0.88 mm2.

COMPACT OPEN-LOOP UWB FILTER WITH NOTCHED BAND

A bandpass filter (BPF) is presented for ultra-wideband (UWB) applications with a notched band to reject the unwanted signals from the wireless local area network (WLAN) systems. The proposed UWB BPF consists of two pairs of open-loop resonators on the top layer and one coupled resonator on the bottom layer. The rejection band is introduced by adding an asymmetric openloop resonator to two outer arms of open-loop resonators. The bandpass filter is designed to be operated within full bandwidth of 3.1 to 10.6GHz and to eliminate the WLAN signals of 5.8GHz. The suppression at 5.8GHz is larger than 15 dB. The proposed configuration is proved to be both simple and compact.

A 1.8- V High-Precision Compensated CMOS Bandgap Reference

A high-precision temperature-compensated ompensated CMOS bandgap reference is proposed and simulated using tsmc 0.18-μm process. The bandgap reference can be operated from a supply voltage as low as 1.8-V. The proposed circuit generates an output reference voltage of 615.1 mV with a variation of ±0.7 mV over a temperature range from 0 to 70°C. The output reference voltage exhibits ± 1mV supply variation from the mean value when the supply changes from 1.6-V to 2.4-V. The power supply rejection ratio is greater than 35 dB for frequency below 10 kHz. The presented bandgap reference occupies only 0.1 mm2 layout area after trimming.

A 1.5-V Low-Power Common-Gate Low Noise Amplifier for Ultrawideband Receivers

A low power ultra-wideband (UWB) common-gate low noise amplifier (CGLNA) for IEEE 802.15.3a is presented. In order to save the power consumption, a current-reuse technology is used. For extending the bandwidth, the proposed circuit uses and the stagger tuning technique of two stacked stages with different resonant frequencies. The circuit is simulated with TSMC 0.18 mum mixed signal/RF CMOS process technology. The post-layout circuit simulation results show the proposed UWB CGLNA can achieve a maximum power gain (S21) of 13.5dB with the -3dB bandwidth from 3.1GHz to 10GHz. The input reflection coefficient S11 and output reflection coefficient S22 are both less than -10dB, a minimum noise figure of 3.55dB, and an input third-order intercept point IIP3 of -6.4dBm. The power dissipation is 2.7mW at 1.5V supply voltage.

A Fast Locking PLL With Phase Error Detector

A fast locking phase-locked loops (PLL) with a phase error detector (PED) circuit is presented. The PED circuit is composed of a dual-slop phase frequency detector and a charge-pump characteristic. The proposed architecture can efficiently reduce both the power dissipation and the acquisition time of the PLL while the loop stability remains unchanged. The proposed PLL is designed in a standard CMOS 0.35μm technology through a 3.3V power supply. The simulation results show that the settling time of the proposed PLL is below 150ns. There is over 50% reduction of the locked time in comparison with the conventional PLLs. The power consumption is 18.5mW at 2.4GHz.

A CMOS Delay-Locked Loop Based Frequency Multiplier for Wide-range Operation

A CMOS delay-locked loop based frequency multiplier is presented. The proposed frequency multiplier can multiply the frequency of input signal without a jitter accumulation problem. Multiplication factor N/2 (N=integer) of the proposed frequency multiplier can be chosen easily according to the number of delay cell and the cascade stage of the multiplier sub-circuits. The frequency mutiplier is simulated using tsmc 0.18 μm CMOS process parameters. The DLL-based frequency multiplier can be operated from 232-MHz to 1.5-GHz with 1.8V supply. The power consumption in the proposed frequency multiplier is 2.215-mW, The DLL core locked time is 4-μs, at 250-MHz. The cycle to cycle jitter of DLL is 10.41-ps.

A 1V fully differential CMOS LNA for 2.4GHz application

In this paper, we present a low voltage CMOS Low Noise Amplifier (LNA) for 2.4GHz application. A folded cascode structure has been used to lower the supply voltage. The proposed circuit has been simulate by using the tsmc 0.18/spl mu/m CMOS process with RF model. When the supply voltage is 1V, the power consumption of the proposed circuit is 9.8mW. At 2.4GHz, the noise figure (NF) is 3.22dB, and the power gain is 15dB.

An Ultra-Wideband LNA with Notch Filter

An ultra-wideband (UWB) common-gate low noise amplifier with notch filter is proposed. For extending the bandwidth, the UWB LNA uses the stagger tuning technique of two stages with different resonant frequencies. The notch filter with extremely high quality factor provides deep rejection ratio to eliminate the in-band interference. The circuit is simulated with TSMC 0.18 mum mixed signal/RF CMOS process technology with 1.8 V power supply. The input reflection coefficient S11 and output reflection coefficient S22 are both less than -10 dB. The flat power gain (S21) is higher than 11 dB while the maximum rejection ratio is over 49 dB at 5.77 GHz. The minimum noise figure is 5 dB.

A 1.5 V 2.4 GHz CMOS mixer with high linearity

An RF mixer with high linearity for 2.4 GHz ISM band applications is presented. The mixer is composed of a modified class-AB transconductor stage and a common mode feedback (CMFB) circuitry. With this topology the following simulation results are achieved: input 1-dB compression point (P-1dB) -8.98 dBm, input third-order intercept point (IIP3) 5.46 dBm, power conversion gain 3.3 dB, and single side-band noise figure 14.87 dB. The mixer implemented by tsmc 0.18 mum CMOS process consumes 3.73 mA of current from a 1.5 V power supply