Yue-Fang Kuo

A 1.8- V High-Precision Compensated CMOS Bandgap Reference

A high-precision temperature-compensated ompensated CMOS bandgap reference is proposed and simulated using tsmc 0.18-μm process. The bandgap reference can be operated from a supply voltage as low as 1.8-V. The proposed circuit generates an output reference voltage of 615.1 mV with a variation of ±0.7 mV over a temperature range from 0 to 70°C. The output reference voltage exhibits ± 1mV supply variation from the mean value when the supply changes from 1.6-V to 2.4-V. The power supply rejection ratio is greater than 35 dB for frequency below 10 kHz. The presented bandgap reference occupies only 0.1 mm2 layout area after trimming.

A CMOS Delay-Locked Loop Based Frequency Multiplier for Wide-range Operation

A CMOS delay-locked loop based frequency multiplier is presented. The proposed frequency multiplier can multiply the frequency of input signal without a jitter accumulation problem. Multiplication factor N/2 (N=integer) of the proposed frequency multiplier can be chosen easily according to the number of delay cell and the cascade stage of the multiplier sub-circuits. The frequency mutiplier is simulated using tsmc 0.18 μm CMOS process parameters. The DLL-based frequency multiplier can be operated from 232-MHz to 1.5-GHz with 1.8V supply. The power consumption in the proposed frequency multiplier is 2.215-mW, The DLL core locked time is 4-μs, at 250-MHz. The cycle to cycle jitter of DLL is 10.41-ps.

Development of receiver and local oscillator components for Atacama large millimeter/submillimeter array (ALMA) band-1 in Taiwan

A series of 31.3-45.0GHz millimeter-wave components including 31.3-45GHz low-noise amplifiers, band-pass and highpass filters, a cascode PHEMT mixer, and 4-12GHz IF amplifiers are developed in Taiwan. The local oscillator for band- 1 is also developed, including the phase-locked GaAs HBT MMIC voltage-controlled oscillator cascaded by a buffer amplifier and a baseline design based on a YIG-tunes oscillator with active frequency doubler. The measured RMS jitter of the HBT VCO LO is around 51 fs and the version of YIG is less than 40fs over 1K to 1MHz frequency offset.

Development of band-1 receiver cartridge for Atacama Large Millimeter/submillimeter Array (ALMA)

The prototype cartridges for ALMA Band-1 receivers have been developed, based on the key components developed in ALMA Band-1 consortium laboratories. The prototype cartridges for each receiver consist of two parts, cold cartridge assembly and warm cartridge assembly. The cold cartridge assembly (CCA) consists of horn antenna, orthomode transducer and a pair of 35-52 GHz cold low-noise amplifiers, the amplified signals of both polarizations are transmitted to warm cartridge assembly by long waveguide sections. In warm cartridge assembly (WCA), two major modules incorporated, down-converter assembly including warm low-noise amplifier, high-pass filter, mixer and 4-12 GHz IF amplifier, and local oscillator based on a 31-40 GHz YIG-tunes oscillator. The frequency range is based on the upper sideband scheme. Based on the measured performance of the key components, the expected noise performance of the receiver will be 26-33K.

A Ka-band YIG-based local oscillator for astronomical heterodyne receiver

A Ka-band local oscillator generator based on YIG-tuned oscillator is designed, fabricated and measured for astronomical telescope applications. The optimized bandwidth analysis can overcome high phase noise problems caused by poor microwave photonic source noise and to improve the outband phase noise of LO by at least 10.5 dB. The experimental results show that the 33.8 GHz LO phase noise of -107 dBc/Hz is achieved at offset frequency of 700 kHz and exhibits a reference spurs of -71 dBc.

A Ka-band offset phase-locked single-tuning VCO with an automatic loop bandwidth calibration

A Ka-band offset phase-locked single-tuning voltage-controlled oscillator (VCO) module with an automatic loop bandwidth (LBW) calibration is designed, fabricated and measured. In this work, the wide tuning range is realized by automatic loop filter selection through self-calibration circuitry. The proposed calibration technique and adaptive LBW theory are used to overcome problems caused by large variation of the VCO tuning sensitivity and to improve the in-band phase noise of phase-locked oscillator (PLO) by at least 17 dB. The experimental results show that the 33.55 GHz PLO phase noise of -97 dBc/Hz is achieved at offset frequency of 200 kHz.

Broadband radio-frequency integrated circuits and modules for astronomical instruments in Taiwan

Various kinds of broadband radio frequency integrated circuits for astronomical instrument were developed in Taiwan during past 18 years. In this paper the key technology and results, including the circuit design, testing, packaging and system integration are described.

Band-1 receiver front-end cartridges for Atacama Large Millimeter/submillimeter Array (ALMA): design and development toward production

The ALMA Band-1 receiver front-end prototype cold and warm cartridge assemblies, including the system and key components for ALMA Band-1 receivers have been developed and two sets of prototype cartridge were fully tested. The measured aperture efficiency for the cold receiver is above the 80% specification except for a few frequency points. Based on the cryogenically cooled broadband low-noise amplifiers provided by NRAO, the receiver noise temperature can be as low as 15 – 32K for pol-0 and 17 – 30K for pol-1. Other key testing items are also measured. The receiver beam pattern is measured, the results is well fit to the simulation and design. The pointing error extracted from the measured beam pattern indicates the error is 0.1 degree along azimuth and 0.15 degree along elevation, which is well fit to the specification (smaller than 0.4 degree). The equivalent hot load temperature for 5% gain compression is 492 - 4583K, which well fit to the specification of 5% with 373K input thermal load. The image band suppression is higher than 30 dB typically and the worst case is higher than 20 dB for 34GHz RF signal and 38GHz LO signal, which is all higher than 7 dB required specification. The cross talk between orthogonal polarization is smaller than -85 dB based on present prototype LO. The amplitude stability is below 2.0 x 10-7 , which is fit to the specification of 4.0 x 10-7 for timescales in the range of 0.05 s ≤ T ≤ 100 s. The signal path phase stability measured is smaller than 5 fs, which is smaller than 22 fs for Long term (delay drift) 20 s ≤ T < 300 sec. The IF output phase variation is smaller than 3.5° rms typically, and the specification is less than 4.5° rms. The measured IF output power level is -28 to -30.5 dBm with 300K input load. The measured IF output power flatness is less than 5.6 dB for 2GHz window, and 1.3dB for 31MHz window. The first batch of prototype cartridges will be installed on site for further commissioning on July of 2017.

Offset phase-locked loop analysis for millimeter-wave local oscillator source

Phase noise estimation of local oscillators using offset phase-locked loops (OPLL) scheme is one of the primary concerns of low-noise millimeter-wave heterodyne receiver design. In this letter, formulations for phase noise model of voltage controlled oscillator (VCO), external signal noise, mixer, and amplifier were derived. OPLLs for two different type of oscillators, one is a GaAs heterojunction bipolar transistor (HBT) single-varactor-tuning voltage-controlled oscillator and the other is a 13-17 GHz YIG-tuned FET oscillators, were characterized and measured to verify the formulation. The measured phase noise and the calculated results based on the derived linear model are well-matched each other, which indicates that the predicted model provides accurate estimation and fast calculation for the OPLL designs.

A 192MHz to1.946GHz Programmable DLL-Based Frequency Multiplier for RF Applications

A delay-locked loop based frequency multiplier is presented using tsmc 0.18 mum CMOS process parameters. The multiplication factor N can be chosen as an integral number whereas the output frequency range is from 192 MHz to 1.946 GHz. The total power consumption is less than 5.8 mW with a 1.8 V supply. The locking time of the DLL core is 0.66 mus at 250 MHz. The cycle-to-cycle jitter of the DLL core is 46 ps.