Robert A. Shearer

Shared buffer having hardware controlled buffer regions

Dynamic virtual software pipelining on a network on chip

Software Pipelining On a Network On Chip

Multithreaded physics engine with predictive load balancing

Cache Utilization Optimized Ray Traversal Algorithm with Minimized Memory Bandwidth Requirements

Network On Chip With Partitions

Method and apparatus for communicating between threads

Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect

Pixel color accumulation in a ray tracing image processing system

Dynamic reallocation of processing cores for balanced ray tracing graphics workload