Russell D. Hoover

Bus architecture employing varying width uni-directional command bus

System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data

Processor-memory bus architecture for supporting multiple processors

System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system

Method and system for transmitting address commands in a multiprocessor system

Snoop filter directory mechanism in coherency shared memory system

Dynamic virtual software pipelining on a network on chip

Method for optimizing reissue commands in master-slave processing systems

Data Cache Invalidate with Data Dependent Expiration Using a Step Value

Method and system for cache coherence despite unordered interconnect transport