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Dive into the research topics where Robert Allinger is active.

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Featured researches published by Robert Allinger.


Applied Physics Letters | 1997

Localized highly stable electrical passivation of the thermal oxide on nonplanar polycrystalline silicon

Hans Jürgen Mattausch; Martin Kerber; Robert Allinger; Helga Braun

A substantial reduction of leakage currents during voltage sweeps from 0 to +20 V is observed for overlap capacitors with polycrystalline silicon (polysilicon) capacitor plates and thermal SiO2 as an insulator. The responsible electrical passivation has a high thermal stability and is localized at the sharp corner, where the upper polysilicon wraps over (overlaps) the lower polysilicon. From baking and recycling electrical-sweep experiments, we conclude that: (1) stability of the localized electrical passivation comes from electrons trapped at deep neutral oxide traps, (2) more than one trap binding energy is involved, and (3) thermal activation energies for electron detrapping, with estimated magnitudes up to 1.3 eV, are about three times larger than previously reported.


IEEE Electron Device Letters | 1998

A degradation mechanism of EEPROM cell operational margins which remains undetected by conventional quality assurance

Hans Jürgen Mattausch; Robert Allinger; Martin Kerber; Helga Braun

We report an electron-discharge mechanism from the floating gate of charged EEPROM cells during the first charging operation after baking (250/spl deg/C, 24 h). For an ensemble of measured EEPROM tells the discharge occurs statistically with threshold-voltage reductions up to over 1 V. Responsible is Fowler-Nordheim (FN) tunneling through the interpolyoxide at the edge where the control gate wraps over the floating gate. This FN tunneling is normally suppressed by a localized highly stable electrical passivation, which is automatically generated by programming operations. Baking partly destroys this passivation so that subsequent cell charging removes more electrons from the floating gate by FN tunneling via the interpolyoxide than it adds via the tunneling oxide.


IEEE Transactions on Electron Devices | 2000

Electrical/thermal properties of nonplanar polyoxides and the consequent effects for EEPROM cell operation

Hans Jürgen Mattausch; Hermann Baumgärtner; Robert Allinger; Martin Kerber; Helga Braun

The electrical/thermal properties of nonplanar polyoxides and the resulting effects for EEPROM operational margins are reported. The polyoxide between floating gate (FG) and control gate (CG) of FLOTOX-type EEPROM cells is nonplanar because it always contains edges, where CG wraps over FG. At such edges a highly stable electrical passivation of Fowler-Nordheim (FN) leakage currents occurs, which can cause a degradation of EEPROM operational margins, due to an electron discharge mechanism from the FG of charged EEPROM cells during the first charging operation after conventional baking. The EEPROM cell study includes the dependence on repeated passivation/depassivation of the polyoxide, on baking temperature and baking time. It is found that the average magnitude of the electron discharge is reduced after each passivation/depassivation cycle, which points to a progressive increase of the number of electrons captured in deep neutral electron traps at the polyoxide edges. Analysis of the temperature dependence leads to an activation energy (thermal detrapping energy of the electrons) of 1.3 eV for the degradation mechanism of EEPROM cell operational margins as well as the nonplanar polyoxide depassivation.


Archive | 2001

Memory device and method for accessing a memory

Heiko Fibranz; Franz-Josef Dipl.-Ing. Brücklmayr; Robert Reiner; Robert Allinger; Klaus Klosa; Robert Hollfelder; Walter Kargl


Archive | 1999

Method of protected access to a memory and corresponding memory device

Robert Allinger; Franz-Josef Dipl.-Ing. Brücklmayr; Heiko Fibranz; Robert Hollfelder; Walter Kargl; Klaus Klosa; Robert Reiner


Archive | 1999

Semiconductor chip with surface covering

Robert Allinger; Wolfgang Pockrandt


Archive | 1998

Semiconductor chip with surface coverage against optical examination of the circuit structure

Robert Allinger; Wolfgang Pockrandt


Archive | 1998

Verfahren und Anordnung zum Betreien eines mehrstufigen Zählers in einer Zählrichtung Method and apparatus for Betreien a multistage counter in a counting

Robert Allinger; Robert Hollfelder; Wolfgang Pockrandt; Armin Wedel


Archive | 1998

Halbleiterchip mit Oberflächenabdeckung gegen optische Untersuchung der Schaltungsstruktur Semiconductor chip having surface coverage against optical inspection of the circuit structure

Robert Allinger; Wolfgang Pockrandt


Archive | 1997

Method for making integrated capacitive structures

Robert Allinger; Helga Braun; Martin Kerber; Hans-Jürgen Mattausch

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