Martin Kerber

Influence of soft breakdown on NMOSFET device characteristics

The degradation of important transistor parameters related to soft breakdown and hard breakdown were studied. Long and short channel transistors were homogeneously stressed at elevated temperature until soft breakdown or hard breakdown occurred. The only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current. This effect arises if the soft breakdown is located within the gate-to-drain overlap region. Soft breakdown generates a spot or path of negative charges in the oxide and therefore enhances gate induced drain leakage current.

Reliability screening of high-k dielectrics based on voltage ramp stress

High-k development moves towards integration into CMOS processes rising attention for the reliability assessment. In this paper, the methodology for reliability screening is discussed based on constant voltage stress and voltage ramp stress. It will be shown that both procedures yield equivalent results and the determined reliability parameters are compatible. Better control of the overall measurement time favours the voltage ramp stress as preferred fast screening method for integration of high-k dielectrics.

Ultra-thick gate oxides: charge generation and its impact on reliability

Abstract In this work, degradation and breakdown characteristics of ultra-thick gate oxides ( T ox : 50–150 nm) used in power MOS devices is investigated. Measurements indicate, that in addition to charge generation via Fowler–Nordheim tunneling, a second mechanism becomes dominant in ultra-thick gate oxides even at moderate electrical fields (i.e. 7–8 MV/cm). The results suggest, that impact ionization and related electron–hole pair creation by energetic electrons is responsible for the experimental observations. The impact of these results on the interpretation of lifetime extrapolations from accelerated tests will be discussed.

Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown

It is shown in this work that the soft breakdown can follow a significantly different temperature and field acceleration behavior than the dielectric breakdown (hard breakdown). These properties have a strong influence on reliability prediction of ultra-thin oxides and can result in misinterpretation if soft breakdown and hard breakdown events are mixed up during gate oxide reliability testing. The activation energy and the field acceleration of the soft breakdown are compared to the disturbed-bond breakage process proposed in the thermochemical E-model. It is concluded that soft breakdown can be caused by H-Si and H-O bond breakage due to the electric field in the oxide. The activation energy for soft breakdown also indicates that formation of a soft breakdown path is influenced by hydrogen diffusion in the oxide.

Influence of gate oxide breakdown on MOSFET device operation

Abstract The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.

Voltage Acceleration of TBD and Its Correlation to Post Breakdown Conductivity of N- and P-Channel MOSFETs

The gate oxide breakdown behavior of advanced n- and p-channel CMOS devices was thoroughly investigated from the time range of electrical overstress events (mus) to package level test conditions (106 s). The voltage acceleration follows the power-law-model over 12 decades in time. In addition the current-voltage driven wear out was studied for linear and non-linear driver elements. It was found that the evolution of the post breakdown conductivity strongly depends on the current limitation and the associated voltage drop across the driving stage. The post breakdown evolution can be described by the intrinsic voltage acceleration model

Lifetime Prediction for CMOS Devices with Ultra Thin Gate Oxides Based on Progressive Breakdown

Progressive breakdown observed in CMOS devices with ultra thin gate oxides can significantly increase the time dependent dielectric breakdown (TDDB) reliability margin of digital CMOS products. The voltage acceleration, the failure distribution of the progressive breakdown and the methodology for quantification of the progressive breakdown is discussed. Extensive experimental data are provided, enabling its implementation

Soft breakdown and hard breakdown in ultra-thin oxides

Abstract Soft breakdown (SBD) and hard breakdown (HBD) events are characterised separate of each other for a 3.4 nm gate oxide. It is shown that both breakdown events can have significantly different voltage and temperature acceleration behaviour. Further it is demonstrated by photoemission microscopy (PEM) for a 2.2 nm oxide that different types of breakdown paths exist. HBD-like and SBD-like breakdowns are found on the same gate area during constant voltage stress. PEM also points out that a structural change of a breakdown path can occur, usually referred to as thermal breakdown of SiO2. It is concluded that a separate characterisation of SBD and HBD events is correct, if the stress conditions do not cause this structural change for the first SBD event.

Gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

The progressive wear-out of a breakdown path in ultra-thin gate oxides depends on oxide thickness and follows the intrinsic voltage acceleration model of time to breakdown. The quantification of progressive wear-out in this work is the critical step towards product relevant assessment of ultra-thin gate oxides.

Reliability aspects of Hf-based capacitors: Breakdown and trapping effects.

Dielectric breakdown and trapping effects are of serious concern for high-k dielectrics. In this paper acceleration models for dielectric breakdown and leakage current degradation in HfSiO films thicker 10 nm are introduced and the mechanism for leakage current increase during constant voltage stress is evaluated.