Robert C. Leachman

An improved methodology for real-time production decisions at batch-process work stations

Demonstrates a methodology which uses the information of future work-in-process (WIP) arrivals to minimize the average number of lots in the queue at a workstation which is capable of processing multiple lots simultaneously as a single batch. This kind of batch-process workstation is common in semiconductor manufacturing; an example is furnace tubes used for deposition operations. The proposed heuristic seeks to minimize the average number of lots waiting in the queue by choosing start times for process cycles that minimize the total lot queue time per unit time over a scheduling horizon equal to the processing time plus any prior waiting time. >

ON CAPACITY MODELING FOR PRODUCTION PLANNING WITH ALTERNATIVE MACHINE TYPES

Analyzing the capacity of production facilities in which manufacturing operations may be performed by alternative machine types presents a seemingly complicated task. In typical enterprise-level production planning models, capacity limitations of alternative machine types are approximated in terms of some single artificial capacitated resource. In this paper we propose procedures for generating compact models that accurately characterize capacity limitations of alternative machine types. Assuming that processing times among alternative machine types are identical or proportional across operations they can perform, capacity limitations of the alternative machine types can be precisely expressed using a formulation that is typically not much larger than the basic linear programming formulation that does not admit alternative resource types. These results have important implications for industrial practice, suggesting that in the case that processing times are nearly proportional among alternatives, the prev...

Benchmarking semiconductor manufacturing

We are studying the manufacturing performance of semiconductor wafer fabrication plants in the US, Asia, and Europe. There are great similarities in production equipment, manufacturing processes, and products produced at these plants. Nevertheless, data reported here show that important quantitative measures of productivity vary by factors of 3 to as much as 5 across an international sample of 16 plants. We conducted on-site interviews with manufacturing personnel to better understand reasons for the observed wide variations in productivity. We have identified factors in the areas of information systems, organizational practices, process and technology improvements, and production control that correlate strongly with productivity.

SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics

SLIM is a set of methodologies and scheduling applications for managing cycle time in semiconductor manufacturing. SLIM includes methodology for calculating target cycle times and target WIP levels for individual manufacturing steps, heuristic algorithms for factory floor scheduling, and optimization-based capacity analysis. Between 1996 and 1999, Samsung Electronics Corp., Ltd., implemented SLIM in all its semiconductor manufacturing facilities. It reduced manufacturing cycle times to fabricate dynamic random access memory devices from more than 80 days to less than 30. Considering the decline of selling prices for dynamic random access memory devices, SLIM enabled Samsung to capture an additional

Modeling train movements through complex rail networks

1 billion in sales revenue compared to the revenue it would have realized had cycle times not been reduced.

An exact solution procedure to determine the optimal dispatching times for complex rail networks

Trains operating in densely populated metropolitan areas typically encounter complex trackage configurations. To make optimal use of the available rail capacity, some portions of the rail network may consist of single-track lines while other locations may consist of double- or triple-track lines. Because of varying local conditions, different points in the rail network may have different speed limits. We formulate a graphical technique for modeling such complex rail networks; and we use this technique to develop a deadlock-free algorithm for dispatching each train to its destination with nearly minimal travel time while (a) abiding by the speed limits at each point on each trains route, and (b) maintaining adequate headways between trains. We implemented this train-dispatching algorithm in a simulation model of the movements of passenger and freight trains in Los Angeles County, and we validated the simulation as yielding an adequate approximation to the current system performance.

Economic Efficiency Analysis of Wafer Fabrication

Trains operating in densely populated metropolitan areas typically encounter complex track configurations. To make optimal use of the available rail capacity, some portions of the rail network may consist of single-track lines whereas other locations may consist of double- or triple-track lines. This paper develops a branch-and-bound procedure that is able to determine the optimal dispatching times for trains traveling in complex rail networks. We demonstrate the efficiency of our branch-and-bound algorithm by comparing it to CPLEX, a commercially available integer program solver, on an actual rail network in Los Angeles County.

A dynamic programming solution to the dynamic, multi-item, single-machine scheduling

Economic efficiency analysis of semiconductor fabrication facilities (fabs) involves tradeoffs among cost, yield, and cycle time. Due to the disparate units involved, direct evaluation and comparison is difficult. This article employs data envelopment analysis (DEA) to determine relative efficiencies among fabs over time on the basis of empirical data, whereby cycle time performance is transformed into monetary value according to an estimated price decline rate. Two alternative DEA models are formulated to evaluate the influence of cycle time and other performance attributes. The results show that cycle time and yield follow increasing returns to scale, just as do cost and resource utilization. Statistical analyses are performed to investigate the DEA results, leading to specific improvement directions and opportunities for relatively inefficient fabs. Note to Practitioners-Speed of manufacturing is an important metric of factory performance, yet it has long been a challenge to integrate its value into overall performance evaluation. However, for many semiconductor products, a predictable rate of decline in selling prices makes it possible to transform time value into monetary value. This study employs a novel method to incorporate a speed metric into economic efficiency evaluation and thereby provide a guideline for improving fab efficiency in manufacturing practice. Furthermore, this study integrates factory productivity and cycle time into a relative efficiency analysis model that jointly evaluates the impact of these two factors in manufacturing performance. In particular, we validate this approach with data from ten leading wafer fabs obtained by the Competitive Semiconductor Manufacturing Program and we discuss managerial implications.

A Simulation Modeling Methodology for Analyzing Large Complex Rail Networks

This article presents a dynamic programming algorithm for scheduling, on a single machine, production of multiple items with time-varying deterministic demands. We formulate the scheduling problem with the objective of minimizing the sum of changeover and inventory holding costs. The formulation is appealing in that it represents changeover costs directly instead of by the familiar approximate technique of including setup costs in the objective. Our algorithm, which we developed using an approach similar to C. R. Glasseys that minimizes the total number of changeovers, casts the optimal schedule as a shortest path through a network embedded in a state space. It generates optimal schedules under two assumptions. First, we assume that in each time period within the planning horizon, the machine must either be shut down or be producing some one item for the entire time period. Second, we assume that inventory holding costs are representable as a nondecreasing function of aggregate inventory. We provide a number of numerical examples that we solved using the algorithm.

Stochastic wafer fabrication scheduling

As the congestion in the nations freeways increases, the reliance on rail freight shipments is increasing. For this reason, models are needed to analyze the increased traffic burden on the rail networks. Compound delays and ripple effects from conflicts at complex junctions, terminals, and railroad-railroad crossings at grade and other factors in some rail networks make it difficult to develop analytical models to study delays and capacity. Therefore, a simulation modeling methodology for analyzing complex rail networks is proposed. The methodology considers both double-track and single-track lines and is insensitive to the size of the rail network. The proposed simulation modeling methodology is then used to analyze train movement from Downtown Los Angeles to the San Pedro Bay Ports.