Robert Darveaux

Effect of simulation methodology on solder joint crack growth correlation

A generalized solder joint fatigue life model for surface mount packages was previously published by the author. The model is based on correlation to measured crack growth data on BGA joints during thermal cycling. It was subsequently discovered by Anderson et. al. that the ANSYS/sup TM/ 5.2 finite element code used in the model had an error in its method for calculating plastic work. It was shown that significant error in life prediction could result by using a recent version of the code where the bug has been fixed. The error comes about since the original crack growth constants were derived based on plastic work calculations that had the bug. In this paper, crack initiation and growth constants are recalculated using ANSYS/sup TM/ 5.6. In addition, several other model related issues are explored with respect to the crack growth correlations. For example, 3D slice models were compared to quarter symmetry models. Anands constitutive model was compared with Darveauxs constitutive model. It was shown that the crack growth rate dependence on strain energy density always had an exponent of 1.10+/-0.15. This is in the range of the original correlation, so the accuracy of relative predictions should still be within+/-25%. However, the accuracy of absolute predictions could be off by a factor of 7 in the worst case, if the analyst uses a modeling procedure that is not consistent with that used for the crack growth correlation. The key to good accuracy is to maintain consistency in the modeling procedure.

Application of through mold via (TMV) as PoP base package

In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.

Model for BGA and CSP reliability in automotive underhood applications

Fine-pitch ball grid array (BGA) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch plastic ball grid array (PBGA) packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the coefficient of thermal expansion (CTE) as measured by thermomechanical analyzer (TMA) typically starts to change at 10-15/spl deg/C lower temperature than the T/sub g/ specified by differential scanning calorimetry (DSC) potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125/spl deg/C. High T/sub g/ substrates with glass-transition temperatures much higher than the 125/spl deg/C high temperature limit, are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveauxs damage relationships were derived on ceramic ball grid array (CBGA) assemblies, with predominantly solder mask defined (SMD) pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than the non solder mask defined (NSMD) pads in thermal fatigue. The thermal mismatch on CBGAs is much larger than PBGA assemblies. Crack propagation in CBGAs is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15, 17, and 23mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-T/sub g/ printed circuit boards. The data has been benchmarked against Darveauxs data on CBGA assemblies. Experimental matrix also encompasses the effect of bis-maleimide triazine (BT) substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

Shear deformation of lead free solder joints

The deformation behavior of lead free solder joints was characterized under shear loading. The test vehicle was a 0.5mm pitch wafer level chip scale package (WLCSP). Five alloys were compared: Sn/sub 63/Pb/sub 37/, Sn/sub 95.5/Ag/sub 4.0/Cu/sub 0.5/, Sn/sub 96.5/Ag/sub 3.0/Cu/sub 0.5/, Sn/sub 96.5/Ag/sub 3.5/, and Sn/sub 99.3/Cu/sub 0.7/. The strain rate range was between 1.0/sec and 10/sup -7//sec, and test temperature was 25C. Both un-aged and thermally aged samples were tested. The aging condition was 24hrs at 125C. At strain rates of 10/sup -2//sec and above, all of the alloys had comparable strength, except for Sn/sub 99.3/Cu/sub 0.7/, which had 20% to 30% lower strength. Sn/sub 63/Pb/sub 37/ was the most strain rate sensitive, and hence had the lowest strength below 10/sup -4//sec strain rate. All alloys showed a 10% to 30% reduction in strength with aging. The solder joints exhibited very high ductility. In some cases strains of 100% were achieved before the joints started to fail. The ductility of Sn/sub 63/Pb/sub 37/ increased with aging, but the ductility of the lead free alloys all decreased with aging. Sn/sub 96.5/Ag/sub 3.0/Cu/sub 0.5/ showed the largest decrease in ductility with aging. The steady state creep behavior observed in the current study is fairly consistent with other published work. However, the absolute value of the joint strength is a little higher than data on bulk samples. All of the alloys exhibited significant primary creep before steady state conditions were achieved. This behavior is not always reported in the literature, and hence it deserves more investigation.

Interface failure in lead free solder joints

The phenomenon of interface failure in lead free solder joints was explored using solder joint array tensile testing. The effects of pad metallization, solder alloy, reflow conditions, and post reflow thermal aging were quantified. The joint strength ranged from 5 to 115MPa. The joint ductility dropped to zero in some cases. The interface microstructure and failure mode were characterized for each combination of factors. Most of the trends were linked to microstructural features of the interface. A ductile-to-brittle transition strain rate (DTBTSR) was defined as a metric to quantify the performance of a specific joint relative to interface failure. The DTBTSR ranged from 10-3 /sec to 10/sec for the conditions studied

Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes

There has been a growing need for fine pitch flip chip technology in support of next generation communication devices with increasing die complexities. The increase in functionality which drives a larger number of signal I/Os in combination with small die size requirements as a result of transistor size reductions have driven the need to investigate finer die interconnect pitches. Traditional solder or Cu Pillar interconnect pitches of 150um to 200um that are currently used in both low and high end flip chip applications are now facing a number of technical limitations as device scaling requirements push the limits of flip chip pad density per square mm of silicon. This paper will review the process development and advancement of several next generation fine pitch Cu Pillar bumping and assembly processes, with pitches less than 60um, that are focused on addressing the challenges seen on silicon nodes such as 65nm and beyond.

Mechanical Properties of Lead-Free Solders

Mechanical testing of solder joint arrays was used to characterize lead-free solder alloys under both shear and tensile loading. The alloys studied included Sn4.0Ag0.5Cu, Sn3.5Ag, Sn0.7Cu, Sn3.0Ag0.5Cu, and Sn1.2Ag0.5Cu0.05Ni. All of the lead-free alloys exhibited time and temperature dependent creep behavior over the entire temperature range from -55 C to 125 C. A SINH creep law was effective in describing the steady state creep behavior over the entire range of conditions. Lead-free alloy strength increases with increasing Ag content. The relative strength of tin-lead versus lead-free alloys depends on the strain rate and temperature regime. At high strain rates and low temperatures, eutectic tin-lead is the strongest alloy. At low strain rates and high temperatures, eutectic tin-lead is the lowest strength alloy. Simulated stress-strain hysteresis loops for both accelerated test and field use conditions showed dramatic differences between the various alloys. Higher Ag content results in a larger stress range but a smaller strain range during temperature cycling.

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

Abstract The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used. Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages. Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40⇔125°C, 15 min ramps, 15 min dwells and 0⇔100°C, 10 min ramps, 5 min dwells.

Ductile-to-brittle transition strain rate

Solder joint failure mode depends on factors such as loading mode (shear vs. tensile), temperature, and strain rate. For any given loading mode and temperature, there is a transition from ductile failure to brittle failure as strain rate is increased. This ductile-to-brittle transition strain rate (DTBTSR) is one of the best indicators for robustness relative to impact loading. A higher value for DTBTSR is better. DTBTSR was measured for a wide range of lead free solder joints. The effects of pad metallization, solder alloy, reflow conditions, thermal aging, test temperature, and loading mode were characterized. DTBTSR was found to improve with 1) electroplated Ni/Au over other finishes (as long as the substrate supplier has a well controlled process), 2) less reflow time above liquidus for Cu pad metallization, 3) mild thermal aging, 4) higher test temperature, and 5) shear loading over tensile loading.

Challenges of megapixel camera module assembly and test

Driven by the market growth of mobile phones with camera, production of image sensor devices has increased dramatically in recent years. From 2004 an increasing number of these mobile phones contain megapixel cameras. The packaging of an image sensor in a camera module presents several unique engineering challenges. Megapixel camera module assembly poses further challenges due to more stringent particle control criteria. For particle control, special attention has to be given on facilities control, equipment and material selection, process flow, discipline among line personnel and continuous particle reduction effort. Other material, process and equipment selection criteria for megapixel module are also discussed. Test for megapixel camera module also has its own challenges. This paper discusses these challenges and methods to meet them.