Robert Floyd Payne

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses these issues.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W for the core ADC.

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs

A 10GS/s 6b time-interleaved ADC in 65nm CMOS is presented in this paper. A partially-active flash sub-ADC structure is proposed to improve the ADC power efficiency and a source-follower based boot-strap T&H circuit is proposed to reduce input kickback and improve the ADC bandwidth. The four-phase 2.5GHz clocks for the sub-ADCs are derived from a 5GHz Nyquist frequency input clock. This leads to accurate timing skew calibration based on duty-cycle calibration, improving the ADC effective resolution at high input frequencies. Measured SNDR is 34.3dB at low input frequencies and 32.0dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83mW with a FOM of 197fJ/conv-step.

A 5Gb/s automatic sub-bit between-pair skew compensator for parallel data communications in 0.13µm CMOS

A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13µm CMOS occupies 0.03mm2 active die area and dissipates 22.5mW.

SE3: Will ADCs overtake binary frontends in backplane signaling?

Receivers with an ADC front end are now competing against conventional receivers with a binary front end, but they consume larger silicon area and possibly larger power. This session discusses the pros and cons and the design tradeoffs between the two approaches in backplane electrical signaling. Each of our five panelists will predict whether the switchover to ADC-based designs will become inevitable.

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS

This paper presents a 10Gbps continuous-time FIR receiver equalizer design with a ¼ symbol-period differential self-biased active inductor delay line in 0.12µm CMOS for wired line data communications. The proposed delay line, together with a proposed active inductor Cherry-Hooper transimpedance load at the FIR filter summing node, increases the equalizer speed, while reducing the equalizer power consumption to only 18mW. The prototype occupies 0.03mm2 die area and measurement results show that the equalizer can compensate for 15dB channel loss at 5GHz for 10Gbps data transmission.

An efficient and resilient ultra-high speed galvanic data isolator leveraging broad-band multi resonant tank electro-magnetic coupling

A novel technology for galvanic data isolation is demonstrated. The integrated high-speed isolated data transfer system-in-package (SIP) supports a maximum data-rate of 2.5Gbps at ~20pJ/bit and is resilient to common-mode-transients (CMTs) >150kV/μs at speeds <;600Mbps, both while meeting a bit-error-rate (BER) of <;10-12. The SIP exceeds the standards body requirements on isolation rating for human safety [1] and extends state-of-art by ~4X in speed and >3X in immunity to CMT [2], [3].

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.