Robert G. Manley

Low Temperature Dopant Activation for Integrated Electronics Applications

A major area of research for integrated electronic systems is the development of systems on glass or plastic. These alternative substrate materials impose significant constraints on electronic device fabrication, including limitations on chemical and thermal processes. This work presents an investigation on the activation of ion-implanted dopants without using the high temperature processes of conventional CMOS. The annealing temperature applied was 600degC, which could potentially enable integrated microelectronics on high-quality glass. Additional factors studied included the annealing technique (furnace or rapid thermal processing), and the use of pre-amorphization implants. Ion-implant modeling along with SIMS and SRP data was used to develop a comprehensive understanding of the experimental results. The performance of transistors fabricated with low-temperature constraints on both bulk silicon and thin- film SOI was presented.

P-197L: Late-News Poster: Demonstration of High Performance TFTs on Silicon-on-Glass (SiOG) Substrate

This report is an introduction to a new silicon-on-glass (SiOG) substrate and device technology. The fabrication and analysis of CMOS devices fabricated using SiOG are presented. The SiOG devices are comparable to those fabricated on SOI wafers with respect to carrier mobility and off-state leakage current. This technology clearly demonstrates the potential for system-on-panel integration.

Investigation on Alumina Passivation for Improved IGZO TFT Performance

A study of the influence of back-channel alumina passivation on the operation of bottom-gate IGZO TFTs is presented. TFTs without any passivation material deposited typically exhibit best-case initial results. Regardless a passivation layer is required for device stability and process integration. The impact of passivation using alumina deposited via electron beam evaporation and atomic layer deposition (ALD) has been investigated. A decrease in subthreshold slope and channel mobility on certain treatment combinations is attributed to an inferior IGZO/alumina back-channel interface. A two-step passivation process has been developed which offers back-channel protection during device fabrication, and remains compatible with an oxidizing ambient anneal. Modifications in the passivation and annealing procedures and process integration details have resulted in a marked improvement in the performance of alumina passivated devices, with demonstrated resistance to aging.

High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs

By utilizing the effects of high energy, or “hot”, electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is proposed to be due to local injection of charge into the gate-oxide at the drain end of the transistor creating a mirror charge in the silicon which mimics an asymmetrical lightly-doped drain structure. An overview of theory, modeling, and device characterization is presented in this study. This effect has been shown to be stable and reproducible; a technique to measure the location and quantity of injected charge is under development.

Demonstration of low temperature CMOS devices on SiOG and SOI substrates

The fabrication and analysis of CMOS devices fabricated on Silicon-on-Glass (SiOG) and compared to SOI (SIMOX) substrates are presented. Key aspects of the low temperature (≪ 600 °C) fabrication process are described. The devices from the SiOG substrate were observed to be comparable to those fabricated on SOI (SIMOX) with respect to carrier mobility and off-state leakage current. SiOG is viewed as a platform with potential applications in advanced flat panel mobile display modules as well as low-cost, medium performance ASICs.