Germain Fenger

Challenges and opportunities in applying grapho-epitaxy DSA lithography to metal cut and contact/via applications

Directed self assembly has become a very attractive technology for Fin and contact/via applications. Some of the issues related to pattern placement error, defectivity rates and process integration are actively being addressed by the industry and have not faced significant roadblocks for contact-hole applications. While many DSA applications have been proposed, deploying DSA for Fin structures competes in cost and variability control with SADP techniques. Given the 1D nature of find structures, it is difficult to control fin placement with accuracy better than 4nm 3 sigma. In addition, a second patterning step is needed to remove the un-wanted sections of the grating and leaving behind only the required fin structures, therefore limiting its adoption. On the other hand, DSA applied to contact/via holes has demonstrated low defectivity rates due to improved polymerization and processing techniques, as well as an adequate control to reduce the placement error due to thermal fluctuations during the annealing and cylinder formation process. For that reason, the results from contact/via layers can extend to the metal cut layer printing with DSA grapho-epitaxy. In this paper, we show that DSA provides a promising cost-effective solution for the technology scaling by reducing mask number from N to N-1. It is shown that pxOPC may provide better guiding patterns than the conventional one. In addition, the practical grouping rules for DSA should avoid 2D grouping, avoid putting more than 3 features in a group with different pitches, and avoid grouping features with different sizes. Our recommendations to designers for DSA technology are the following: if the design is to be decomposed with 2 or more DSA masks, then the design rules should be set up in this way: first the minimum pitch is better to be on DSA material’s own natural pitch; second, for each DSA mask, singletons and bar-like grouping shapes with DSA’s natural pitch should be used as much as possible.

Flare in extreme ultraviolet lithography: metrology, out-of-band radiation, fractal point-spread function, and flare map calibration

The critical role of flare in extreme ultraviolet (EUV) lithography is well known. In this work, the implementation of a robust flare metrology is discussed, and the proposed approach is qualified both in terms of precision and accuracy. The flare measurements are compared to full-chip simulations using a simplified single fractal point-spread function (PSF), and the parameters of the analytical PSF are optimized by comparing the simulation output to the experimental results. After flare map calibration, the matching of simulation and experiment in the flare range from 4 to 12% is quite good, clearly indicating an offset of about 3%. The origin of this offset is attributed to the presence of DUV light. An experimental estimate of the DUV component is found in good agreement with the predicted value.

Calibration and application of a DSA Compact model for graphoepitaxy hole processes using contour-based metrology

Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.

Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes

This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Full chip correction of EUV design

Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model has been validated in the full flare range available within the mask. The model calibration yielded an RMS of about 1nm, and a EUV mask fully corrected for OPC, flare and shadowing was finally fabricated and qualified.

Implementation of templated DSA for via layer patterning at the 7nm node

In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7nm node. At this node the DSA technology could alleviate costs for double patterning and limit the number of masks that would be required per layer. At imec multiple approaches for inserting DSA into the 7nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA (grapho-epitaxy), since hole patterns are readily accessible through templated hole patterning of cylindrical phase BCP materials. Here, the pre-pattern template is first patterned into a spin-on hardmask stack. After optimizing the surface properties of the template the desired hole patterns can be obtained by the BCP DSA process. For implementation of this approach to be implemented for 7nm node via patterning, not only the appropriate process flow needs to be available, but also appropriate metrology (including for pattern placement accuracy) and DSA-aware mask decomposition are required. In this paper the imec approach for 7nm node via patterning will be discussed.

N7 logic via patterning using templated DSA: implementation aspects

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7 nm node. At this node the DSA technology could alleviate costs for multiple patterning and limit the number of masks that would be required per layer. At imec, multiple approaches for inserting DSA into the 7 nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA; a grapho-epitaxy flow using cylindrical phase BCP material resulting in contact hole multiplication within a litho-defined pre-pattern. To be implemented for 7 nm node via patterning, not only the appropriate process flow needs to be available, but also DSA-aware mask decomposition is required. In this paper, several aspects of the imec approach for implementing templated DSA will be discussed, including experimental demonstration of density effect mitigation, DSA hole pattern transfer and double DSA patterning, creation of a compact DSA model. Using an actual 7 nm node logic layout, we derive DSA-friendly design rules in a logical way from a lithographer’s view point. A concrete assessment is provided on how DSA-friendly design could potentially reduce the number of Via masks for a place-and-routed N7 logic pattern.

Compact model experimental validation for grapho-epitaxy hole processes and its impact in mask making tolerances

There has been significant research in the area of modeling self-assembling molecular systems. Directed self-assembly (DSA) has proven to be a promising candidate for cost reduction of processes which use double patterning and an enabler of new technology nodes. Self-consistent field theory and Monte Carlo simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-b-PMMA diblock copolymer system needs. The compact model’s main objectives are to find the guiding pattern that produces the lowest possible placement error, as well as verifying that the intended target structures are present after processing. Given that masks are not perfect, and lithographic process variations are not negligible, it is necessary to understand the mask requirements and the types of Optical Proximity Correction techniques that will be used to build guiding patterns. This paper explores the guiding pattern conditions under which proper assembly is achieved, and how the compact model formulation is able to determine placement of reliably assembling structures as well as identification of the guiding patterns which lead to improper assembly. The research leading to these results has been performed in the frame of the industrial collaborative consortium IDeAL focused on the development of Directed Self-assembly technique by block copolymers.

Design correction in extreme ultraviolet lithography

Extreme ultraviolet (EUV) lithography is currently the most promising technology for advanced manufacturing nodes. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool using the latest Interuniversity Microelectronics Center baseline resist Shin-Etsu SEVR59. In total ~1300 critical dimension (CD) measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32 nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The reticle used in this calibration exercise allowed one to modulate flare by varying tiling densities. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different types through pitch and CD were used to calibrate the shadowing correction. The model calibration yielded an root-mean square of ~1 nm, which was observed to improve by including reticle CD data. An EUV mask fully corrected for optical proximity correction, flare and shadowing was fabricated and qualified, demonstrating the effectiveness of the implemented corrections.