Robert Hsieh

Dual side lithography measurement, precision, and accuracy

Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution, and improved process control for pattern placement on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of lithographic systems. The requirements for an advanced DSA metrology tool include the capability of measuring points over the entire area of the substrate, and of measuring a variety of different substrates and film types and thicknesses. This paper discusses the precision and accuracy of an advanced DSA metrology system, the UltraMet 100. This system offers DSA registration measurement at greater than 90% of a wafers surface area, providing a complete front to back side registration evaluation across a wafer. The system uses top and bottom cameras and a pattern recognition system that allow simultaneous target capture and measurement on both substrate surfaces. Because no industry standard has been established to determine the accuracy of dual side pattern metrology, an accuracy gauge was designed for this study that allows both top and bottom cameras to simultaneously measure offsets between two targets on one substrate surface. In this paper, an accuracy gauge is measured on the UltraMet 100 and the results are compared to measurements taken on a reticle X/Y pattern placement metrology tool calibrated to a NIST traceable standard. In addition, tool performance is analyzed in terms of system repeatability and reproducibility.

Large area interposer lithography

Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from 1.5 to 4.0 μm in width are evaluated to measure critical dimension (CD) control where the lines cross the subfield boundaries. CD metrology at the bottom and top of the photoresist is performed using a top down CD-SEM. Finally large area test interposers are patterned using two subfields on a 1X stepper and processed through a Cu electroplating module for detailed characterization. The CD control of routing lines as they cross the subfield boundary can be optimized by using a shaped or tapered line end design. Lithography simulation using Prolith modeling software by KLA-Tencor is matched to experimental results and then used to evaluate performance of various line end designs. Larger latitude for overlap error was observed for the tapered line end compared to the standard square line end. The experimental and modeled results in this study show the capability of using stepper lithography to produce large area interposers with 1.5 μm I/O routing line dimensions.

Lithography technique to reduce the alignment errors from die placement in fan-out wafer level packaging applications

The rapid growth of wireless consumer electronics products is driving demand for cost effective and small form factor packaging solutions. While front end silicon technologies have followed Moores law by device scaling, the back end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on silicon is significantly higher than the speed achieved on the printed circuit boards. Innovative advancements such as Fan-out wafer level packaging technology were introduced to address the pad limitation consideration with traditional wafer level packaging while delivering miniaturization and potential low cost packaging advantages. It does this by extending the package interconnect area beyond the front end chip size to allow increased number of I/O required for large die sizes. This technology allows tested-good dice to be reconstituted into wafer form, and interconnections are formed using wafer level processing technology. Die positioning control within the reconstituted wafer significantly affects downstream process requirements. The use of high productivity pick and place equipment with multiple gantries create challenges for the lithographic tool alignment when die placements from each gantry are not identical. This will be especially true in the future as the placement tolerances are reduced for advanced products containing multiple die types. This paper describes the inaccuracy in pick and place from single and dual gantry operation, and investigates lithographic alignment methods specifically developed to minimize pick and place errors from multiple gantry operation. The current single zone alignment algorithm was extended to create multiple selection zones to match the multiple gantries of the die pick and place equipment. The enhanced capability allows the flexibility to conduct a separate alignment mapping for different zones of the reconstituted Fan-out wafers. The dual zone mapping gave more effective compensation for a gantry matching error, resulting in better than 50% improvement in registration error compared with a single zone mapping. This provides significantly superior alignment control for next generation devices fabricated with fan out wafer level packaging process.

Overlay performance of through Si via last lithography for 3D packaging

Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include both the TSV critical dimension (CD) and overlay variations. In this paper we investigate the long term capability of a Dual Side Alignment (DSA) lithography system for printing 5 μm and smaller TSV features. DSA lithography is used to pattern the TSV feature, and Stepper Self Metrology (SSM) is performed to verify the overlay after photoresist development. Multiple stepper lithography fields per wafer and multiple wafers per lot are measured to obtain a statistically significant data set for wafer lot overlay analysis. In addition, multiple wafer lots were processed and measured to establish long term overlay performance and stability. In order to independently verify the SSM overlay data, dedicated electrical structures were designed and placed on a Via Last TSV test chip. These structures allow the TSV diameter and TSV overlay to be measured electrically after lot completion. Vector plots were used to compare the SSM overlay and electrical overlay data.

Development and characterization of a 300-mm dual-side alignment stepper

A number of new packaging technologies are driving the demand for high performance dual-side alignment (DSA) on 300 mm lithography systems. Advanced system in package (SiP) techniques will require through silicon vias to allow very high density vertical interchip wiring of multiple device stacks. These through silicon vias need to be freely placed in the device which creates a requirement for tight registration of the back-to-front side alignment. In the MEMS area, wafer level packaging is being used for applications where the device must interact with the outside environment without performance restrictions from the packaging. An example is image sensor chips where the charge-coupled device is on the front side and the electrical interconnects to the signal processing die are on the back side. This application requires dual-side alignment on a 300 mm bonded silicon glass sandwich structure. To support these packaging applications a new lithography stepper capable of dual-side alignment on 300 mm wafers has been developed. This stepper employs an innovative and flexible system for back-to-front side alignment to support a wide range of packaging applications. This paper discusses the design and integration of the alignment system on a broad band, low numerical aperture stepper. Experimental target capture for CMOS image sensor applications is shown. Dual-side overlay performance data on multiple wafers and lots is reviewed.