Robert J. Landers

A flexible gate array architecture for high-speed and high-density applications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAMs feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.

A multiplexer-based architecture for high-density, low-power gate arrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology. >

A flexible gate array for high speed and high density applications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides a 2.5/spl times/ density improvement, 30% speed-up, and 70% lower power. NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAMs feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.