Shivaling S. Mahant-Shetti

High performance low power array multiplier using temporal tiling

Digital multipliers are a major source power dissipation in digital signal processors. Array architecture is a popular technique to implement these multipliers due to its regular compact structure. High power dissipation in these structures is mainly due to the switching of a large number of gates during multiplication. In addition, much power is also dissipated due to a large number of spurious transitions on internal nodes. Timing analysis of a full adder, which is a basic building block in array multipliers, has resulted in a different array connection pattern that reduces power dissipation due to the spurious transition activity. Furthermore, this connection pattern also improves the multiplier throughput. This array pattern is based on creating a compact tiled structure, wherein the shape of a tile represents the delay through that tile. That is, a compact structure created using these tiles is nothing but a structure with high throughput. Such a temporal tiling technique can also be applied to other digital circuits. Based on our simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier. Improvement in delay can be traded for power using voltage reduction techniques.

The log-log LMS algorithm

This paper describes a new variant of the least-mean-squares (LMS) algorithm, with low computational complexity, for updating an adaptive filter. The reduction in complexity is obtained by using values of the input data and the output error, quantized to the nearest power of two, to compute the gradient. This eliminates the need for multipliers or shifters in the algorithms update section. The quantization itself is efficiently realizable in hardware. The filtering section is unchanged. Thus, this algorithm is similar to the sign based variants of the LMS algorithm. However, the complexity of the proposed algorithm is lower than that of the sign-error LMS algorithm, while its performance is superior to this algorithm. In particular, it is close to that of the regular LMS algorithm. The new algorithm also requires much lower area for ASIC implementation.

A multiplexer-based architecture for high-density, low-power gate arrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology. >

A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an O.8 /spl mu/m CMOS process is described. The interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules including a center-of-mass defuzzification, may be computed in 2 /spl mu/sec.<<ETX>>

Microstructure isolation testing using a scanning electron microscope

A new form of testing is described that is suitable for verifying isolation in many forms of microstructures. Excess charge is deposited on the microstructures by a scanning electron microscope (SEM) beam. On elements of the microstructures that are isolated, this excess charge induces a voltage contrast that is detected at the same time by the same beam. Isolation to approximately 2×1011 Ω can be verified. The method is simple and fast, requiring only a standard SEM and simple test structures.

Memory based digital signal processing

A cost-effective approach to increasing the processing throughput of many digital signal processing (DSP) systems is described.. This movement is achieved by migrating some of the basic computational elements to memory. The classic Von Neumann bottleneck is circumvented by localizing the computations to memory, and a high throughput is achieved by exploiting the memory architecture. For certain DSP applications that require a simple type of operation to be applied to a large amount of data, e.g. pattern recognition or matrix-matrix multiplications, the increase in throughput is very high. It is also shown that a system built with these memories is easier to use than systolic arrays or multiprocessor systems. As examples, compared to conventional solutions, a 10* improvement is shown for a continuous speech recognizer and a 16* improvement for a 128*128 matrix multiplication. Higher-orders-of-magnitude improvements are possible for larger problems and more memory chips.<<ETX>>

Using scanned electron beams for testing microstructure isolation and continuity

Scanned electron beams provide a superior method of testing for isolation and continuity in integrated circuit microstructures by observing the voltage contrast generated by charge storage on isolated nodes. The authors discuss how such beams can be used to test, ICs during the manufacturing steps to insure proper pattern transfer and isolation and, to a more limited degree, continuity. The method uses the electron beam as the active probe to both drive and test the device. Under the proper conditions, the beam can deposit charge on nodes of the IC. Nodes which are isolated change potential and exhibit voltage contrast with respect to the nodes that are fixed in potential. Thus, the beam also instantly reads out the success or failure of the isolation of a node. Examples are shown from silicon-on-insulator (SOI) mesas and from novel test structures for checking patterning fidelity in polysilicon and metal layers.<<ETX>>