Robert L. Wisnieff

Wafer-scale epitaxial graphene growth on the Si-face of hexagonal SiC (0001) for high frequency transistors

Up to two layers of epitaxial graphene have been grown on the Si-face of 2 in. SiC wafers exhibiting room-temperature Hall mobilities up to 2750 cm2 V−1 s−1, measured from ungated, large, 160×200 μm2 Hall bars, and up to 4000 cm2 V−1 s−1, from top-gated, small, 1×1.5 μm2 Hall bars. The growth process involved a combination of a cleaning step of the SiC in a Si-containing gas, followed by an annealing step in argon for epitaxial graphene formation. The structure and morphology of this graphene has been characterized using atomic force microscopy, high resolution transmission electron microscopy, and Raman spectroscopy. Furthermore, top-gated radio frequency field-effect transistors (rf-FETs) with a peak cutoff frequency fT of 100 GHz for a gate length of 240 nm were fabricated using epitaxial graphene grown on the Si-face of SiC that exhibited Hall mobilities up to 1450 cm2 V−1 s−1 from ungated Hall bars and 1575 cm2 V−1 s−1 from top-gated ones. This is by far the highest cutoff frequency measured from any...

Display technology: Printing screens

The paperless office has been predicted as a result of electronic information systems, but now paper is fighting back. A cheap electronic ink has been developed that can be printed on flexible substrates, including paper. It can be changed from white to black simply by applying an electric field, and so it could be used to make paper that can print on itself or show moving pictures.

Effect of SiC wafer miscut angle on the morphology and Hall mobility of epitaxially grown graphene

We show that the surface morphology and electrical properties of graphene grown on SiC(0001) wafers depend strongly on miscut angle, even for nominally “on-axis” wafers. Graphene grown on pit-free surfaces with narrow terraces (miscut above 0.28°) shows substantially lower Hall mobility than graphene on surfaces with miscut angles below 0.1° that have wider terraces with some pits. The effect of pits on mobility is not detrimental if flat, pit-free areas with dimensions larger than the carrier mean free path remain between pits. Using these results, we optimized the growth process, achieving room-temperature mobility up to 3015 cm2/V s at N=2.0×1012 cm−2.

Functional testing of TFT/LCD arrays

Introduction Of all the flat-panel technologies, only the TFT/LCD is expected to pose a serious challenge to the cathode ray tube [1]. TFT/LCD prototypes have already demonstrated full color capability, a requirement of high-informationcontent displays. TFT/LCDs also have an inherent immunity to high ambient light levels while operating at low levels of power consumption, a characteristic not shared by electroluminescent or plasma displays. Many companies have recognized the advantages of the TFT/LCD, and the total investment in this technology is now approaching two billion dollars [2]. TFT/LCD technology shares many similarities with silicon integrated circuit technology, such as djoiamic random access memories (DRAMs). Both involve film deposition, although TFT/LCD technologies employ lowertemperature processing. In both, photolithography and etching are used to pattern each level. Both structures employ random addressing capability. Many characterization and yield management techniques are also applicable to both. The operating mode of a TFT/LCD is not digital, however, but analog, because the light output varies as a smooth function of the voltage stored [3]. Therefore, functional testing of TFT/LCDs is much different, as will be seen. There is growing interest in testing and repair techniques for these displays [4-8]. We have developed a Dynamic Array Tester that characterizes TFT arrays. The Dynamic Array Tester can detect, locate, and grade both line faults and pixel faults in a TFT array. It can be used as an in-line manufacturing screen to sort product into pass, fail, or repair categories, and this sorting can be done immediately after the arrays have been fabricated and again after the display has been filled with liquid crystal. It can also be used to verify array designs and perform failure analysis.

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

A 10.5-in.-diagonal SXGA active-matrix display

A 157-dot-per-inch, 262K-color, 10.5-in.- diagonal, 1280 × 1024 (SXGA) display has been fabricated using a six-mask process with Cu or Al-alloy thin-film gates. The combination of high resolution and gray-scale accuracy has been shown to render color images and text with paperlike legibility. The low-resistivity gate metallization and trilayer-type TFTs with a channel length of 6-8 µm were fabricated with a six-mask process which is extendible to larger, higher-resolution displays. A combination of double-sided driving and active line repair was used so that open gate lines or data lines did not result in visible line defects. A flexible drive-electronics system was developed to address the display and characterize its performance under different drive conditions.

Electronic displays for information technology

The principal channel of interactive communication from a computer to a person is an electronic display. The amount of information shown and the way in which it can be exhibited depend on successfully matching the capabilities of the display to the human visual system. Making this channel as wide, as fast, and as effective as possible has been the goal of electronic display development for the last fifty years. The cathode ray tube (CRT), which has been the dominant display device used in offices and homes, is the display device on which the personal computer and the graphical user interface were developed. Today, the capabilities of information technology are brought to new environments by new display technologies. Active-matrix liquid crystal displays (AMLCDs) have freed the personal computer from the desktop, projection displays bring the power of information technology into meetings, small liquid crystal displays have allowed the development of hand-held computers, and head-mounted displays are bringing wearable computer technology onto the factory and warehouse floor.

A six-mask TFT-LCD process using copper-gate metallurgy

— A novel reduced mask process is used to fabricate high-resolution high-aperture-ratio 10.5-in. SXGA (1280 × 1024) displays. The process uses copper gate-metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150-dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high-resolution displays that are suitable for notebook applications.

Multilayer epitaxial graphene formed by pyrolysis of polycrystalline silicon-carbide grown on c-plane sapphire substrates

We use ultrahigh vacuum chemical vapor deposition to grow polycrystalline silicon carbide (SiC) on c-plane sapphire wafers, which are then annealed between 1250 and 1450 °C in vacuum to create epitaxial multilayer graphene (MLG). Despite the surface roughness and small domain size of the polycrystalline SiC, a conformal MLG film is formed. By planarizing the SiC prior to graphene growth, a reduction in the Raman defect band is observed in the final MLG. The graphene formed on polished SiC films also demonstrates significantly more ordered layer-by-layer growth and increased carrier mobility for the same carrier density as the nonpolished samples.

Interconnect issues post 45nm

Despite many projections on the inevitable post-PVD evolution of interconnect technology, it remains PVD-based for liner-seed through 45 nm and perhaps farther, with an ALD process change the obvious next step perhaps followed by a switch from Ta to Ru. Cu size effects are not critical to low-level (1times) line RC and the biggest performance opportunity is with the high level fat lines. CA technology, both barrier and fill, does not scale well and may evolve to more interconnect-like materials, potentially unifying two tooling areas