William F. Richardson

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

A 4Mb DRAM with cross point trench transistor cell

This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

Trench capacitor design issues in VLSI DRAM cells

Major issues involved in the optimization of trench capacitors for VLSI DRAMs are considered, using the previously described 4Mb DRAM cross-point Trench-Transistor Cell (TTC) as a vehicle. The effects of capacitor plate doping, trench etch angle and depth on the capacitance of the trench capacitor are studied. Pisces-II simulations show that there is adequate electrical isolation between adjacent cells, with a grounded substrate. Any tendencies for intercell leakage are further minimized, by reverse-biasing the substrate at-2.0V. High-resolution TEM and lattice imaging techniques are utilized to study the quality of oxide dielectric in the trench capacitor. In addition, a simple way of enlarging the capacitor area, in order to increase the storage capacitance, is presented.

Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L/sub DD/ structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 /spl mu/m CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance.

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

High performance sub-half micron CMOS using rapid thermal processing

A sub-half micron CMOS technology has been developed using rapid thermal processing (RTP) and a simplified process design. The threshold voltages are set high to permit operation above room temperature without excessive leakage. Novel process features include zero-topography well design, RTP CMOS well anneal in an ammonia ambient, RTP gate oxide, RTP source/drain anneal, and BPSG reflow at 750 degrees C in a high-pressure nitrogen ambient. Transistors with 8 nm gate oxide and 0.4 mu m gate lengths provide 65 ps gate delay at 3.3 V. The use of 4*10/sup 17//cm/sup 3/ CMOS well doping without added channel implants results in higher diode capacitance and increases inverter chain delay by approximately 20 ps/stage, but speeds less than 50 ps/stage should be obtained with L=0.3 mu m NMOS and L=0.4 mu m PMOS, both having effective channel lengths of approximately 0.2 mu m.<<ETX>>

Polysilicon transistors in VLSI MOS memories

The recent progress on the use of as-deposited, small grain LPCVD polysilicon transistors in VLSI memories is discussed with the emphasis on their applications for static and dynamic RAMs. Some process and device related issues are discussed. Successful implementation of an experimental stacked CMOS 64K sRAM proves the utility of these devices for three dimensional integration in a VLSI environment.

Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm2using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAMs.