Robert Tu

Berkeley reliability tools-BERT

Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in todays and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented. >

An AC conductance technique for measuring self-heating in SOI MOSFET's

In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFETs from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFETs that demonstrate that heating can indeed be significant in SOI devices.<<ETX>>

A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation

An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, Delta I/sub D/ is implemented as an asymmetrical voltage-controlled current source and the new Delta I/sub D/ model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented. >

AC output conductance of SOI MOSFETs and impact on analog applications

We report a frequency-dependent output conductance of partially depleted SOI MOSFETs. For high-frequency analog applications, the output conductance is less than half and the dynamic range of V/sub d/ is two times higher than the dc I-V characteristics would indicate. A simple physical model for the phenomenon that involves a phenomenological body charging capacitance and can fit data within 10% is presented.

Simulating process-induced gate oxide damage in circuits

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator.

A new approach for simulation of circuit degradation due to hot-electron damage in NMOSFETs

The authors present a novel approach for modeling hot-electron-induced change in drain current for both forward and reverse modes of operation. The change in drain current, Delta I/sub D/, is implemented as an asymmetrical voltage-controlled current source. The authors first present the physical basis of the model and derive the analytical model equations. the implementation scheme for the analytical Delta I/sub D/ model in the BERT (Berkeley Reliability Tool) simulator and a detailed evaluation of the model as a function of different device and circuit parameters are also given. Simulation results of unidirectional and bidirectional circuits based on the new model are presented.<<ETX>>

A comparative study of advanced MOSFET structures

This work presents a comparative study of advanced MOSFET structures that have been proposed for around 0.1 /spl mu/m generation in the subjects of short-channel effect, drain saturation current, and relative gate delay. Our approach differs from other studies in that we emphasize compact analytical models and parametric comparison. These heuristic and analytic models are guided by experimental and simulational data. Based on these models, key device design parameters are extracted and compared. This approach provides good insight for device design, quick figure-of-merit, and a framework for analyzing a wide variety of MOSFETs. The devices in this study are : (a) uniformly-doped MOSFET, (b) delta-doped MOSFET, (c) pocket-implanted MOSFET, (d) SOI MOSFET, and (e) double-gated MOSFET. Their generic extensions cover almost every advanced MOSFET.

SOI MOSFET modeling using an AC conductance technique to determine heating

SOI technology is a prospect for future integrated circuits. It allows increased circuit speeds, simple device isolation, elimination of latchup, etc. However, SOI MOSFETs are susceptible to localized heating effects which reduces mobility and thus MOSFET current. We propose a new SPICE model for SOI MOSFETs which takes into account self-heating. Using an AC conductance measurement technique, we have isolated the MOSFETs IV without self-heating. Using the BSIM3 MOSFET model, we are able to model the heating-free IV characteristics. We use an RC circuit to model the heating and adjust the mobility accordingly.

Simulating radiation reliability with BERT

Abstract This paper describes a simulator which can be used to study the effects on circuit behaviour of two radiation phonomena: Single Event Upset (SEU) and total-dose radiation effects. The core of the device is BERT (BErkeley Reliability Tools), an IC reliability simulator. The SEU simulator uses an established methodology, but a novel choice of sensitive nodes is made, which allows a fast simulation of very large circuits. The total-dose simulator predicts circuit behaviour after a user-specified radiation dose using an ordinary circuit simulator, such as SPICE. Simulation results are compared to actual experimental data.