Dennis Sinitsky

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

To extend the lower bound of power supply to ultra-low voltages (0.6 V and below), we propose a dynamic-threshold voltage MOSFET (DTMOS) built on silicon-on-insulator (SOI). The threshold voltage of DTMOS drops as the gate voltage is raised, resulting in a much higher current drive than standard MOSFET at low power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide experimental results and 2-D device and mixed-mode simulations to analyze DTMOS and compare its performance with a standard MOSFET. These results verify excellent DC inverter characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for DTMOS.<<ETX>>

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V.<<ETX>>

High-field transport of inversion-layer electrons and holes including velocity overshoot

In this paper, we experimentally address the effect of a wide range of parameters on the high-field transport of inversion-layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, vertical field strength, nitridation of the gate oxide, and device channel length. We employ special test structures built on Silicon-On-Insulator (SOI) and bulk wafers to accurately measure the high-field drift velocity of inversion-layer carriers. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocities on nitridation of the gate oxide, dependence of the high-field drift velocity on the effective vertical field, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness.

Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications

With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the device performance in terms of current driving capability and switching speed. Recently MOSFET devices whose threshold voltages can be adapted during the transistor operation using the body effect have been proposed for low voltage and low power VLSI applications. In these devices, the threshold voltages are reduced by forward-biasing the body-to-source junction. In this paper we study the effect of the channel doping engineering on this threshold voltage reduction scheme.

AC output conductance of SOI MOSFETs and impact on analog applications

We report a frequency-dependent output conductance of partially depleted SOI MOSFETs. For high-frequency analog applications, the output conductance is less than half and the dynamic range of V/sub d/ is two times higher than the dc I-V characteristics would indicate. A simple physical model for the phenomenon that involves a phenomenological body charging capacitance and can fit data within 10% is presented.

High field hole velocity and velocity overshoot in silicon inversion layers

We report measurements of the drift velocity of holes in silicon inversion layers. The saturation velocity of holes at 300 K is found to be strongly dependent on the effective vertical field. No hole velocity overshoot was observed down to 0.16 /spl mu/m channel length at room temperature. At 77 K, hole velocity saturation is much less pronounced, and a 10% higher average velocity is observed for 0.16 /spl mu/m channel length as compared to 0.36 /spl mu/m channel length.

Velocity overshoot of electrons and holes in Si inversion layers

Abstract Velocity overshoot of inversion layer electrons and holes is studied experimentally and analytically in special test structures with nominally uniform electric field. The data were used to calibrate energy relaxation parameters in a commercial simulator MEDICI ver. 2.0. We propose an analytical model for velocity overshoot and show that it agrees well with experimental data. The amount of hole velocity overshoot is small.

Saturation velocity and velocity overshoot of inversion layer electrons and holes

In this paper we address the effect of a wide range of parameters on the high-field transport of inversion layer electrons and holes. The studied parameters include substrate doping level, surface micro-roughness, nitridation of the gate oxide, and device channel length. Our findings point to electron velocity overshoot at room temperature, dependence of electron and hole saturation velocity on nitridation of the gate oxide, and relative insensitivity of electron and hole mobility and saturation velocity to moderate surface roughness.<<ETX>>

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L/sub eff/ below 0.2 /spl mu/m.