Francesco Rezzi

Low-voltage analog filters

This paper reviews the design of analog filters at low supply voltage. In particular, the main focus is on switched capacitor and g/sub m/-C type filters because, at the present time, they have the greatest commercial importance. SC implementations are discussed in the context of low frequency high precision applications while g/sub m/-C implementations are discussed in the context of high frequency medium/low precision applications. Both fundamental and practical limitations to the achievable dynamic range at low supply voltage are explained. The paper reviews well established circuit and architectural techniques as well as some promising new ones that might result in performance improvements in the future.

A 3 V 12-55 MHz BiCMOS pseudo-differential continuous-time filter

The reduction of the supply voltage forces one to develop system and circuit solutions able to achieve the same performance previously obtained with higher supply voltage. In this paper, a second-order low-pass continuous-time filter operating at a 3 V power supply is presented. The prototype filter is implemented using a highly linear pseudo-differential transconductor. The input common-mode signal is canceled at the transconductor level using a feed-forward path. The output common mode voltage is controlled at the filter level using lossy integrators. A prototype cell has been realized in 1.2 /spl mu/m BiCMOS technology. The pole frequency can be tuned in the range 12-55 MHz. A THD of -40 dB is achieved for signals up to 1 V/sub pp/ at 10 MHz. The dynamic range is approximately 60 dB.

A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization

A seventh-order phase equiripple continuous time filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read channel applications is presented. The 7-50 MHz cutoff frequency, amount of boost, and group-delay slope are programmable via 7-b digital-to-analog converters (DACs). At 50 MHz fc, power consumption is 70 mW and output swing for 1% distortion is more than 500 mVpp. The transconductance capacitance (Gm-C) filter is built in a 0.7-/spl mu/m 10-GHz BiCMOS technology.

A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters

This paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third-order system with a bandwidth of 100 kHz and a lock-in time of 15 /spl mu/s. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm/sup 2/.

Novel linearization circuit for BiCMOS transconductors used in high frequency OTA-C filters

A novel linearization circuit for a tunable BiCMOS transconductor based on the emitter degeneration of bipolar devices is analyzed. The transconductor is suitable for high-frequency continuous-time filter implementations because of the large value of the gm/I ratio and its ease of tunability. An integrator cell with a unity gain bandwidth of up to 80 MHz can be realized with a capacitive load as large as 3 pF and a power consumption of about 3.5 mW. An extended tuning range can be achieved through the proposed linearization circuit that reduces the total harmonic distortion (THD) in the lower part of the tuning range. Simulation program with IC emphasis (SPICE) simulation results are presented, comparing the classical solution with respect to the linearized one; the input stage shows an output current THD less than 1% for an input differential signal of up to 500m V/sub pp/ over an almost 10:1 tuning range.<<ETX>>

Design of high-frequency BiCMOS continuous-time filters with low-output impedance transconductor

A design approach for realizing high-frequency Gm-C continuous-time filters is proposed and a circuit implementation is presented. The design approach is based on reducing the effects of the finite impedance at each output node by placing a controlled output active load whose value is taken into account in the filter design. The implementation uses a BiCMOS high-efficiency fully-differential transconductor with an all-passive common-mode feedback. Simulation results of a biquadratic low-pass filter with cut-off frequency up to 82 MHz and load capacitance as large as 3pF conclude the paper.<<ETX>>

Low-power BiCMOS continuous-time shaping filter

A biquadratic continuous-time filter designed to operate as signal shaper in the read-out electronics of elementary particles experiments has been implemented in 2 /spl mu/m BiCMOS technology. The cell synthesizes a semi-Gaussian response with a shaping time adjustable in the range 18-30 ns. The power consumption is 1.25 mW from a single 5 V power supply. The integral nonlinearity is within 1% for an input signal amplitude up to 200 mV. The chip active area is 0.08 mm/sup 2/. The measured input referred noise is 50 nV//spl radic/Hz.

Designing Analog IC at University of Pavia

The importance and the effectiveness of any actions can be better assessed looking at the long-term results that derived from the original actions associated with it. This is what we are going to see in this paper, where we want to celebrate the research and education activity of Prof. Rinaldo Castello in the Microelectronics Lab at University of Pavia, where all of us have been students starting (in same cases) more than 25 years ago.

Session 22 overview / analog: DC/DC converters

Summary form only given. Market trends today are driving for highly efficient power conversion in high volume portable applications. This highlights the need for high-level single-chip integration of DC-DC converters in leading edge processes with other signal-path systems. This high-level of integration is driven by system cost and form factor. Moreover, system performance and cost and special design challenges at these advanced process nodes require taking into account the voltage and reliability limitations of nanometer technologies on switching converter designs. While power efficiency is of paramount importance, other system issues are driving new methods for design robustness and ease of test. The speakers in this session present the latest integration efforts and novel techniques to improve the performance and cost of DC-DC converters.

A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver

VDSL2 transceivers use a wide analog bandwidth to achieve bit-rates in excess of 200Mb/s. For standard 6-band VDSL2, 30MHz bandwidth is required, comprising three up-stream and three down-stream signals. Since discrete multi tone (DMT) modulation is used, distortion components for the signal chain have to be below −65dBc to fully exploit 15b-per-tone bit loading [1].