Robertus D. J. Verhaar

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

Self-aligned CoSi2 and TiW(N) local interconnect in a submicron CMOS process

Abstract The integration aspects of a self-aligned CoSi 2 and TiW(N) local interconnect technology in a submicron CMOS process are described. The effect of substrate type and dope on the final sheet resistance of CoSi 2 has been investigated. A small influence of the dope concentration has been observed on the formation of CoSi, however no significant effect is measured on the sheet resistance of the finally formed CoSi 2 . The CoSi reaction has been found to be very sensitive to the SiCo interface condition. A sacrificial oxidation has proven to be a suitable method to ensure a proper reaction. An electrical testing method is presented, which has shown to be a very sensitive method to detect overgrowth (bridging) in the salicide process. Voltage contrast SEM analysis showed to be suitable to locate overgrowth. The use of the CoSi 2 salicide process did not provoke any serious degradation of transistor performance or gate oxide integrity. The results are comparable with those of TiSi 2 . TiW(N) is reported to be a good material for local interconnect in combination with CoSi 2 . The integration aspects of the TiW(N) local interconnect technology are discussed. The etching process of TiW(N) appears to be the most critical step.

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.