Andrew Jan Walker

A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions

Abstract The transistor parameters of state-of-the-art MOSFETs are affected by quantisation effects of the carrier motion in the inversion channel. To account for these effects in classical device stimulators, we show that a better modeling of the silicon bandgap at inversion conditions is ifE g QM = E g CONV + 13 9 Δϵ in which Δϵ is the position of the first energy level with respect to the bottom of the conduction band. The improved modeling of the bandgap leads to a new model for the intrinsic carrier concentration ni. The model for ni has been tested against measurements and against self-consistent QM calculations. Excellent agreement is obtained.

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Shallow boron junctions and preamorphization for deep submicron silicon technology

In this study, shallow p+‐n junction diodes were formed by implanting BF+2 ions into single‐crystal silicon or silicon preamorphized by either Si or Ge implantation. BF+2 implantation at energies of 20 or 25 keV and a dose of 1×1015 cm−2 was followed by furnace annealing at 600 °C in nitrogen ambient. Most samples received a further nitrogen‐ambient anneal at 850 °C, with various periods of time. Secondary ion mass spectroscopy was used to measure the B profiles. Cross‐sectional transmission electron microscopy was used to study the amorphous layers and the defects remaining after annealing. Electrical characterization of the diodes is described. In preamorphized samples, the residual defect density decreases, and the defect band located at the original amorphous‐crystalline interface becomes sharper, as the mass of the amorphizing ion species is increased. Ideal low‐leakage shallow junctions can be made following either Si or Ge preamorphization and furnace annealing, without removing all the defects ind...

Quantum-mechanical threshold voltage shifts of MOSFETs caused by high levels of channel doping

The impact of high doping levels on the threshold voltage of MOS transistors is discussed. The threshold voltage of surface channel devices is shown to be affected through the quantum-mechanical splitting of the energy levels in the conduction band. A significant threshold voltage shift is reported at room temperature for deep-submicron n-channel devices and needs to be taken into account in the design of the devices. A simple analytical model to account for this effect is proposed.<<ETX>>

Effects of high normal electric fields in deep submicron MOSFET's

The implications of high normal electric fields in MOSFETs on device simulations are discussed. Comparison of simulations with data of experimental MOS devices shows that, even at room temperature, the electric fields generated by high levels of channel doping affect the threshold voltage by quantum-mechanical effects. Furthermore, the surface mobility is reduced by high normal fields, but can still be modeled accurately when calculated as a function of the effective electric field.

Shallow P + -Junction Technology for 0.25 μm CMOS

A preamorphisation technology for fabrication of shallow p⁺-junctions for 0.25 μm CMOS was studied. Silicon and germanium ions were used for preamorphisation. A low energy BF<inf>2</inf>⁺ implantation was used for the formation of the p⁺-region. The physical (SIMS,XTEM) and electrical characterisation of shallow p⁺-junctions will be presented. Large p⁺-diodes and 0.25 μm PMOS transistors were fabricated. The best results were obtained for Ge preamorphised material. Low leakage current p⁺-junctions with depth of 0.15 μm were obtained. However, the preamorphisation technology is complex, has a small process window for shallow p⁺-junctions and the benefits over a conventional approach are not significant. Excellent results were obtained for shallow p⁺ junctions (0.18 μm) fabricated with conventional BF<inf>2</inf>⁺ implants with reduced implantation energy and thermal budget.

Device Characterisation of a High-Performance 0.25 μm CMOS Technology

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage of a non-optimized 51-stage ringoscillators fabricated in the 0.25 μm process was 62 ps at 2.5 V supply voltage which is a 1.5 times improvement over the delay obtained in a 0.5 μm CMOS technology at 3.3V.