P.A. van der Plas

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

New developments for the digital compact cassette system

The introduction of a small portable digital compact cassette (DCC) player has been made possible by the development of a new 18-channel head and associated new read electronics. Special attention needs to be paid to the equalization of the signals, as this depends on the tape direction during recording and playback, as well as the degree of asymmetry of the head design. The configuration of head and ICs described is applied in headphone stereo and car players. >

Profile engineering for sub-micron CMOS using high energy ion implantation

An improved implantation scheme has been developed for a submicron retrograde twin-well CMOS (complementary metal-oxide-semiconductor) process. A blanket p-well implantation is used to avoid one photoresist step. The use of a phosphorus compensating implantation for PMOS (p-channel MOS) transistor threshold voltage control avoids another resist step and photoresist processing on gate oxide. The latter results in an improved gate oxide integrity. The new implantation scheme has been successfully employed in the fabrication of a 1-Mb SRAM (static random-access memory) on 150-mm wafers.<<ETX>>

Geometry Dependent Bird's Beak Formation for Submicron LOCOS Isolation

Birds beak formation is one of the major problems for LOCOS field isolation. In this paper we demonstrate that the birds beak length is not a constant, but depends strongly on geometry of the oxidatioin mask for submicron mask dimensions. The birds beak length can vary up to a factor of 4, dependent on mask geometry. Four independent geometry effects are distinguished and their impact on an IC-process is discussed.

A 1M SRAM with full CMOS cells fabricated in a 0.7&#181;m technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.