Roderick Dr Mcconnell

How we test Siemens Embedded DRAM Cores

The techniques used to test Siemens Embedded DRAM Cores are described. Test Isolation and Design-For-Test logic is built in to the core interface, while external access and Algorithmic Pattern Generation are handled by a central Test Controller. All tests used for standard DRAMs can be applied to the DRAM cores, but only a subset of these are used for any given product.

From behavioral to RTL models: an approach

Presents an approach for developing register transfer level (RTL) system models from behavioral models. Synchronous data flow principals are used to assist the transition. Our approach is based on a model of synchronous VLSI components which describes both their behavior, and their timing diagrams at a register transfer level. The component model permits the verification of correct synchronization at a system level. Initialization and termination conditions are explicitly checked.<<ETX>>

Prototyping of VLSI components from a formal specification

A trajectory from formal specification to component is presented, which can be used to prototype applications which combine off-the-shelf components and custom hardware, provided they meet the constraints of Synchronous Data Flow. The formal specification allows one to prove that custom components will be correctly synchronized in a system context. VLSI Synchronous Data Flow is introduced, the constraints it imposes are elaborated, and functions relevant to constructing a system are defined. Then, a component for motion video coding in VHDL is developed and synthesized, starting from a formal specification.