Romain Esteve

Surface-Passivation Effects on the Performance of 4H-SiC BJTs

In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100°C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

Advanced oxidation process combining oxide deposition and short postoxidation step for N-type 3C- and 4H-SiC

The electrical properties of oxides fabricated on n-type 3C-SiC (001) and 4H-SiC (0001) epilayers using an advanced oxidation process combining plasma enhanced deposition and rapid postoxidation steps have been investigated. Three gas atmospheres have been studied for the postoxidation steps: N2O, dry, and wet oxygen (H2O). In comparison, additional oxides using postannealing in pure N2 have been fabricated. The implementation of wet oxygen resulted in a significant decrease in the interface traps density, in a reduction of oxide fixed charges and in the increased breakdown field in the case of 3C-SiC. In the case of 4H-SiC the postoxidation in N2O is a superior postprocessing step.

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Comparative study of thermally grown oxides on n-type free standing 3C-SiC (001)

Alternative ways to improve the oxidation process of free standing 3C-SiC (001) are developed and tested with the aim to reduce the fixed and mobile charges in the oxide and at the SiO2/3C-SiC inte ...

High Quality 3C-SiC Substrate for MOSFET Fabrication

Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm-1.

Experimental evaluation of different passivation layers on the performance of 3kV 4H-SiC BJTs

In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

MOS Capacitors Fabricated on 3C-SiC(111) Layers Grown on 6H-SiC(0001)

In this work we report on the various steps, from growth to processing, required for the fabrication of metaloxide-semiconductor (MOS) capacitors using 3C-SiC(111) material and with superior interfacial quality. The layers were first heteroepitaxially grown by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate. Then the surface was polished before homoepitaxial thickening by chemical vapour deposition. On such 3C-SiC material, the MOS capacitors were fabricated using an advanced oxidation process combining Plasma-Enhanced Chemical Vapour Deposition of SiO 2 and short post-oxidation steps in wet oxygen (H 2 O:O 2 ). Electrical measurements of these MOS capacitors led to very low density of interface traps, D it = 1.2 x 10 10 eV ―1 cm ―2 at 0.63 eV below the conduction band, and fixed oxide charges Q eff /q estimated to ―7 x 10 9 cm ―2 . These characteristics, which are, to the authors knowledge, the best values found for SiC based MOS capacitors, represent a significant advance towards the fabrication of MOS devices based on 3C-SiC.

3C-SiC MOS Based Devices: From Material Growth to Device Characterization

In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (Dit)can be drastically decreased down to 1.2  1010 eV-1cm-2 at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.

Performance and ruggedness of 1200V SiC — Trench — MOSFET

This paper describes a novel SiC trench MOSFET concept. The device is designed to balance low conduction losses with Si-IGBT like reliability. Basic features of the static and dynamic performance as well as short circuit capability of the 45mΩ/1200 V CoolSiC™ MOSFET are presented. The favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in. Long-term gate oxide tests reveal a very low extrinsic failure rate well matching the requirements of industrial applications.

An electrical and physical study of crystal damage in high-dose Al- and N-implanted 4H-SiC

In this paper, an investigation into the crystal structure of Al-and N-implanted 4H-SiC is presented, encompassing a range of physical and electrical analysis techniques, with the aim of better understanding the material properties after high-dose implantation and activation annealing. Scanning spreading resistance microscopy showed that the use of high temperature implantation yields more uniform resistivity profiles in the implanted layer; this correlates with KOH defect decoration and TEM observations, which show that the crystal damage is much more severe in room temperature implanted samples, regardless of anneal temperature. Finally, stress determination by means of μRaman spectroscopy showed that the high temperature implantation results in lower tensile stress in the implanted layers with respect to the room temperature implantation samples.