Romano Hoofman
Philips
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Publication
Featured researches published by Romano Hoofman.
IEEE Transactions on Device and Materials Reliability | 2006
J. Michelon; Romano Hoofman
In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is higher for more porous SiOC low-k materials, and its presence inside the low-k has a strong impact on the dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased; in addition, higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires maximum attention to prevent moisture uptake at each step during integration; in addition, the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability
international interconnect technology conference | 2003
Rudy Caluwaerts; M. Van Hove; Gerald Beyer; Romano Hoofman; H. Struyf; G.J.A.M. Verheyden; Joost Waeterloos; Zsolt Tokei; Francesca Iacopi; L. Carbonell; Quoc Toan Le; Arabinda Das; Ingrid Vos; S. Demuynck; Karen Maex
The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.
international reliability physics symposium | 2004
Zsolt Tokei; Victor Sutcliffe; Steven Demuynck; Francesca Iacopi; Philippe Roussel; Gerald Beyer; Romano Hoofman; Karen Maex
The purpose is to show that TDDB reliability of damascene structures has to be assessed as a system composed of a dielectric, copper diffusion barrier and copper. This becomes mandatory when porous low-k materials are considered, since barrier integrity is a key contributor in TDDB behavior. Solely addressing the dielectric properties is not adequate. When a not fully dense barrier is considered the apparent dielectric properties are degraded due to copper migration into the dielectric.
MRS Proceedings | 2006
Aurelie Humbert; Didem Ernur Badaroglu; Romano Hoofman
The degradation of SiOC(H) low-k films upon plasma treatments has been investigated. Different generations of SiOC(H) low-k dielectrics (k=3.0 and k=2.6) were used. The low-k materials have been exposed to N /sub 2/O, NH/sub 3/, O/sub 2/, H/sub 2/, He, Ar and N/sub 2/ based plasmas, representing the most commonly-used plasmas during interconnect integration. Some of the experiment points were also carried out on a highly porous SiOC material (k=2.3), for additional comparison. For all plasma-treated samples, an increase in k-value and decrease in breakdown voltage was observed. These observations could be attributed to chemical degradation, in particular to carbon depletion and OH-bond formation. The latter leads to moisture adsorption, which was confirmed by contact angle measurements and FTIR spectra. The N/sub 2/O plasma treatment was found Io be the most aggressive for all low-k dielectrics studied. It drastically increases the k-value and the leakage current and results in complete carbon removal on the top-surface. This effect is most pronounced on the most porous material. On the other hand, an in-situ helium plasma shortly after low-k deposition enhances the resistance to chemical degradation upon exposure to other plasmas, even for the most aggressive ones. For the argon and reactive pre-clean plasmas, only small compositional changes were observed. In conclusion, it can be said that not only the plasma treatments have to be tuned in accordance with the low k integration requirements, but also attention has to be paid to limit moisture absorption during integration.
international reliability physics symposium | 2006
J. Michelon; J. Waeterloos; P.H.L. Bancken; V.h. Nguyen; Rudy Caluwaerts; Gerald Beyer; S. Rozeveld; E. Beach; Romano Hoofman
As device dimensions scale down, the back-end-of-line dimensions scale down as well, which results in an increasing resistance-capacitance delay of the interconnect. In order to compensate for the increase in the capacitance part, porous low-k dielectrics have been introduced in copper interconnect technology. Due to the highly interconnected pore structure of most porous low-k materials, liquid and/or gaseous species fill the pores of the matrix during integration steps. In addition, pores give rise to surface roughness at the top-interface and at the sidewall after etch, which makes it difficult to deposit a thin, continuous barrier in narrow trenches embedded in porous low-k dielectrics. All of the above makes pore sealing a prerequisite for reliable porous low-k integration (Guedj et al., 2004). Different pore sealing techniques are under investigation. In the case of low-k materials in which the porosity is created using a porogen, the porosity creation could also be shifted to a later phase of the integration scheme; either after low-k etch (Caluwaerts et al., 2003) or after metal CMP (Fayole et al., 2004; Jousseaume et al., 2005), which is referred to as post-etch-burn-out (PEBO) and post-CMP-burn-out (PCBO), respectively. It has been demonstrated previously, that the dielectric reliability could be improved considerably by these kinds of pore sealing techniques (Tokei et al., 2004). In this paper, both integration approaches are compared for porous SiLKtrade dielectric resin (k=2.2) from The Dow Chemical Company and the effect of both integration approaches on the interline capacitance, the dielectric reliability and electromigration are investigated and discussed in more detail
international interconnect technology conference | 2006
A. Ikeda; Youssef Travaly; A. Humbert; Romano Hoofman; Yunlong Li; Zs. Tokei; Francesca Iacopi; J. Michelon; Christophe Bruynseraede; M. Willegems; Dirk Hendrickx; J. Van Aelst; H. Struyf; J. Versluijs; Nancy Heylen; L. Carbonell; O. Richard; Hugo Bender; M. Kaiser; R.G.R. Weemaes; G.J.A.M. Verheyden; N. Kemeling; A. Fukazawa; N. Matsuki; Hessel Sprey; Ivan Ciofi; G. Beyer; M. Van Hove
Single damascene (SD) Cu/Aurorareg ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, which enables to perform the resist ash before dielectric etch. This patterning scheme is used in combination with a low damage etch technique based on sidewall protection. Interconnect performance and reliability can be further improved by using Aurorareg ULK high modulus (HM), a low-k film with a reduced diffusivity as compared to Aurora ULK, and a comparable k-value of 2.7. The MHM approach results in a limited increase in integrated k-value by 0.1 for ULK HM vs. 0.3 for Aurorareg ULK. The median time dependent dielectric breakdown (TDDB) lifetime is well above the 10 years criterion for spacings down to the 50nm. Finally, the MHM integration scheme enabled fabrication of dual damascene interconnects with Aurorareg ULK HM
Microelectronic Engineering | 2005
Romano Hoofman; G.J.A.M. Verheijden; J. Michelon; Francesca Iacopi; Youssef Travaly; Mikhail R. Baklanov; Zs. Tokei; Gerald Beyer
Archive | 2010
Aurelie Humbert; Romano Hoofman
Microelectronic Engineering | 2004
Y. Furukawa; R.A.M. Wolters; H.H.A.J. Roosen; J.H.M. Snijders; Romano Hoofman
Microelectronic Engineering | 2005
L.G. Gosset; A. Farcy; J. de Pontcharra; Ph. Lyan; Roel Daamen; G.J.A.M. Verheijden; V. Arnal; Frederic Gaillard; D. Bouchu; P.H.L. Bancken; T. Vandeweyer; J. Michelon; V. Nguyen Hoang; Romano Hoofman; J. Torres