J. Michelon

Moisture influence on porous low-k reliability

In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is higher for more porous SiOC low-k materials, and its presence inside the low-k has a strong impact on the dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased; in addition, higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires maximum attention to prevent moisture uptake at each step during integration; in addition, the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability

The impact of scaling on interconnect reliability

Back-end-of-line (BEOL) reliability, comprising barrier, dielectric and current-carrying metal reliability, is a major challenge for future IC generations as the reliability margin of the dielectric/barrier/copper systems is shrinking. The impact of interconnect scaling on BEOL reliability is outlined and illustrated by low-k TDDB, electromigration and stress-induced-voiding results.

Self Aligned Barrier Approach: Overview on Process, Module Integration and Interconnect Performance Improvement Challenges

Self aligned barriers approaches are widely investigated because they lead to a strong improvement of the Cu/barrier interface adhesion generally considered as the limiting factor for the electromigration performance of Cu interconnects capped with dielectric barriers. In this paper, several ways to perform self aligned barrier integration, using either Cu line surface treatments or selective deposition process on top of Cu lines and their basic performance are detailed. Achieved electrical and reliability performance are discussed in terms of process, integration feasibility and related issues, and architecture (stand-alone or bi-layered stack) since the self aligned barriers can be introduced at different levels of complexity depending on the performance targets and the applications foreseen

Comprehensive electromigration studies on dual-damascene Cu interconnects with ALD WC/sub x/N/sub y/ barriers

Am important improvement in electromigration (EM) resistance was revealed upon the introduction of atomic-layer-deposited WCN barriers in dual-damascene Cu interconnects. At stress level EM failure were found to increase with WCN thickness and to be consistently superior compared to I-PVD deposited barriers. Although the voiding scenario is identical for both ALD and I-PVD barriers, a reduction of the current density exponent and the activation energy is observed for ALD. In contrast to the influence of WCN barrier thickness on the EM behaviour, the effect of specific pre-clean procedures prior to the ALD process turned out to the less pronounced.

Reliability Characterization of Different Pore Sealing Techniques on Porous Silk Dielectric Films

As device dimensions scale down, the back-end-of-line dimensions scale down as well, which results in an increasing resistance-capacitance delay of the interconnect. In order to compensate for the increase in the capacitance part, porous low-k dielectrics have been introduced in copper interconnect technology. Due to the highly interconnected pore structure of most porous low-k materials, liquid and/or gaseous species fill the pores of the matrix during integration steps. In addition, pores give rise to surface roughness at the top-interface and at the sidewall after etch, which makes it difficult to deposit a thin, continuous barrier in narrow trenches embedded in porous low-k dielectrics. All of the above makes pore sealing a prerequisite for reliable porous low-k integration (Guedj et al., 2004). Different pore sealing techniques are under investigation. In the case of low-k materials in which the porosity is created using a porogen, the porosity creation could also be shifted to a later phase of the integration scheme; either after low-k etch (Caluwaerts et al., 2003) or after metal CMP (Fayole et al., 2004; Jousseaume et al., 2005), which is referred to as post-etch-burn-out (PEBO) and post-CMP-burn-out (PCBO), respectively. It has been demonstrated previously, that the dielectric reliability could be improved considerably by these kinds of pore sealing techniques (Tokei et al., 2004). In this paper, both integration approaches are compared for porous SiLKtrade dielectric resin (k=2.2) from The Dow Chemical Company and the effect of both integration approaches on the interline capacitance, the dielectric reliability and electromigration are investigated and discussed in more detail

Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

Single damascene (SD) Cu/Aurorareg ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, which enables to perform the resist ash before dielectric etch. This patterning scheme is used in combination with a low damage etch technique based on sidewall protection. Interconnect performance and reliability can be further improved by using Aurorareg ULK high modulus (HM), a low-k film with a reduced diffusivity as compared to Aurora ULK, and a comparable k-value of 2.7. The MHM approach results in a limited increase in integrated k-value by 0.1 for ULK HM vs. 0.3 for Aurorareg ULK. The median time dependent dielectric breakdown (TDDB) lifetime is well above the 10 years criterion for spacings down to the 50nm. Finally, the MHM integration scheme enabled fabrication of dual damascene interconnects with Aurorareg ULK HM