Youri Victorovitch Ponomarev

Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology

We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 /spl mu/m devices are manufactured using p- and n-type poly-Si/Si/sub 0.8/Ge/sub 0.2/ gates.

Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge/sub 0.3/Si/sub 0.7/) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, /spl phi//sub B/, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q/sub bd/) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

High hole mobilities in fully-strained Si/sub 1-x/Ge/sub x/ layers (0.3<x<0.4) and their significance for SiGe pMOSFET performance

Materials studies, hole transport measurements, and process and device simulations have been employed to determine the optimum epitaxial architecture of a fully-pseudomorphic Si/SiGe pMOSFET heterostructure that is intended for application in a near-standard CMOS process. Numerical simulations have shown that SiGe inter-diffusion severely limits the Ge content that can be achieved in a practical process flow. The SiGe hole wave-functions have been calculated and it is shown that hole confinement effects become very significant for SiGe layers less than 5 nm thick. Furthermore, estimates of the barrier penetration by the hole wave-function indicate that the beneficial effects of the buried-channel structure upon the hole mobility would be significantly reduced for Si cap thickness less than 2 nm. Buried-channel SiGe pMOSFETs are known to suffer from parallel conduction in the Si capping layer and calculations of the charge distribution indicate that high Ge contents (>30%) and thin Si cap thickness (<3 nm) are required in order to confine all of the inversion charge to the SiGe layer. The hole drift mobility has been measured at room temperature for fully-strained Si/sub 1-x/Ge/sub x/ layers with a range of alloy contents (0.3<x<0.4), and with hole densities between 3/spl times/10/sup 11/ cm/sup -2/ and 4/spl times/10/sup 12/ cm/sup -2/. The measured room temperature mobilities are consistently higher than the equivalent Si inversion layer mobilities and these results have been incorporated into two-dimensional (2-D) device simulations in order to understand their significance for SiGe pMOS device performance. It is found that improvements in current drive can be obtained, but only for the most aggressive vertical architectures. For Si cap thickness greater than 1.5 nm, parallel conduction in the cap layer counteracts much of the advantage of the high mobility channel and, even for thin Si caps, velocity saturation effects at high lateral electric fields significantly limit the current drive of a SiGe pMOSFET to values close to that of the conventional Si device. The diminished gate control, due to the inclusion of the cap layer, and the smaller SiGe bandgap also lead to a significant deterioration of the subthreshold characteristics.

Detailed modeling of sub-100-nm MOSFETs based on Schro/spl uml/dinger DD per subband and experiments and evaluation of the performance gap to ballistic transport

We analyze in detail the requirements for the detailed physical modeling of nanoscale MOSFETs and show that Schro/spl uml/dinger drift-diffusion per subband simulations are adequate for the inverse modeling of bulk-Si MOSFETs with gate length down to 40 nm (channel length down to 26 nm) from their dc electrical characterization. We show that a proper treatment of quantum effects both in the channel and in the polysilicon gate through the direct solution of Schro/spl uml/dinger equation, and a transport model based on two-dimensional subbands are required for accurate and-after calibration-predictive modeling. The model is included in the NANOTCAD2D code (Curatola and Iannaccone, 2003). We also evaluate the performance gap to ballistic transport, by comparing the experiments with simulations based on a fully ballistic transport model on the devices structures extracted with the inverse modeling procedure.

Drift mobilities and Hall scattering factors of holes in ultrathin Si1−xGex layers (0.3<x<0.4) grown on Si

Sheet resistivity and Hall measurements have been performed on a series of p-type modulation-doped Si/Si1−xGex heterostructures. The structures were grown by a production-compatible atmospheric-pressure chemical-vapor deposition technique and all the epitaxial layers were lattice matched to the silicon substrates. A depleted-doping technique was used to supply the quantum well with holes, and this approach has enabled the transport properties of the SiGe layers to be characterized between 4.2 and 295 K. Measurements of the Hall scattering factor and drift mobility are reported for ultrathin, high-Ge content layers (0.3<x<0.4) with a range of hole densities up to 4×1012 cm−2. The drift mobilities are shown to be substantially and consistently higher than comparable mobilities reported for holes in Si/SiO2 inversion layers. A drift mobility of 460±20 cm2/V s was measured at 295 K for a 6 nm-thick Si0.65Ge0.35 layer. This is more than a factor of 2 greater than the equivalent Si inversion layer mobility and ...

A 0.13 /spl mu/m poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

A manufacturable 25 nm planar MOSFET technology

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

Pre-amorphization and co-implantation suitability for advanced PMOS devices integration

now at Philips Semiconductors, Crolles, France

A Manufacturable Sub-50nm PMOSFET Technology

One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.