Ronald D. Blanton

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior

DIAGNOSIX is a comprehensive fault diagnosis methodology for characterizing failures in digital ICs. Using limited layout information, DIAGNOSIX automatically extracts a fault model for a failing IC by analyzing the behavior of the physical neighborhood surrounding suspect lines. Results from several simulated and over 800 failing ICs reveal a significant improvement in localization. More importantly, the output of DIAGNOSIX is an accurate model of the logic-level defect behavior that provides useful insight into the actual defect mechanism. Experiment results for the failing chips with successful physical failure analysis reveal that the extracted faults accurately describe the actual defects

Development of a MEMS testing methodology

Microelectromechanical systems (MEMS) are miniature electromechanical sensor and actuator systems developed from the mature batch-fabricated processes of VLSI technologies. Projected growth in the MEMS market requires significant advances in CAD and manufacturing for MEMS. These advances must be accompanied with testing methodologies that ensure both high quality and reliability. We describe our approach for developing a comprehensive testing methodology for a class of MEMS known as surface micromachined sensors. Our first step involving manufacturing process and low-level mechanical simulations is illustrated by studying the effects of realistic contaminations on the folded-flexure comb-drive resonator. The simulation results obtained indicate that realistic contaminations can create a variety of defective structures that result in a wide spectrum of faulty behaviors.

Analyzing the effectiveness of multiple-detect test sets

Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec

Analysis of failure sources in surface-micromachined MEMS

cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.

Virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits

The effect of vertical stiction, foreign particles, and etch variation on the resonant frequency of a surface-micromachined resonator and accelerometer are presented. For each device, it is shown that misbehaviors resulting from different failure sources can overlap, exhibit dominance and combine to create behavior masking and construction. Such an analysis is essential for developing test and diagnosis methodologies for surface-micromachined MEMS.

CAEN-BIST: testing the nanofabric

In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing [15]-[17] to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse structure in (spatial) frequency domain, VP achieves substantially lower sampling frequency than the well-known (spatial) Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate that by testing the delay of just 50 chips on a wafer, VP accurately predicts the delay of the other 219 chips on the same wafer. In this example, VP reduces the estimation error by up to 10× compared to other traditional methods. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids — Verification General Terms Algorithms

Universal fault simulation using fault tuples

A built-in self-test algorithm is developed for chemically-assembled electronic nanotechnology (CAEN) that exploits reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This algorithm is particularly suited for regular architectures with high defect densities.

Diagnostic Test Generation for Arbitrary Faults

We introduce a new fault representation mechanism for digital circuits based on fault tuples. A fault tuple is a simple 3-element condition for a signal line, its value, and clock cycle constrain t. AND-OR expressions of fault tuples are used to represent arbitrary misbehaviors. A fault simulator based on fault tuples was used to conduct experiments on benc hmark circuits. Simulation results show that a 17% reduction of average CPU time is achiev ed when performing sim ulation on all fault types simultaneously, as opposed to individually. We expect further improvements in speedup when the shared characteristics of the various fault types are better exploited.

Built-in self test of CMOS-MEMS accelerometers

It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in any diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout

Deformations of ic structure in test and yield learning

A built-in self-test technique for MEMS that is applicable to symmetrical microstructures is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically-located points. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and manufacturing process variations.