Wojciech Maly

Inductive Fault Analysis of MOS Integrated Circuits

Inductive Fault Analysis (IFA) is a systematic Procedure to predict all the faults that are likely to occur in MOS integrated circuit or subcircuit The three major steps of the IFA procedure are: (1) generation of Physical defects using statistical data from the fabrication process; (2) extraction of circuit-level faults caused by these defects; and (3) classification of faults types and ranking of faults based on their likelihood of occurrence Hence, given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics. The IFA procedure is illustrated by its applications to an example circuit. The results from this sample led to some very interesting observations regarding nonclassical faults.

Built-in current testing-feasibility study

A testing methodology which applies built-in current sensors to detect abnormal currents in the power buses of functional blocks of CMOS ICs is proposed, that significantly improves the quality of VLSI circuit testing. A summary of simulation results and design experiments is presented to demonstrate the feasibility and to illustrate the applicability of the approach. The results suggest that built-in current testing could be a very powerful tool for overcoming basic bottlenecks in VLSI testing, providing very inexpensive testing, high-quality built-in testing, or on-chip concurrent reliability testing for high-quality fault-tolerant systems.<<ETX>>

CMOS bridging fault detection

The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of directly expressing many of the likely CMOS faults, was still able to generate a set of effective test patterns. Current monitoring, however, by virtue of its more accurate model and less stringent detection criterion, was able to generate tests of measurably higher quality. It is concluded that the selection of one technique over the other becomes a cost tradeoff. Current testing produced test patterns that were consistently more effective in detecting bridging faults. This higher quality comes at higher start-up costs aid higher costs per chip design.<<ETX>>

Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

VLSI Yield Prediction and Estimation: A Unified Framework

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented. >

Interconnect characteristics of 2.5-D system integration scheme

Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing chip size. To address this problem instead of placing all systems components in one layer (i.e. in 2-D space) one can use a stack of single layer monolithic ICs (called here a 2.5-D integrated IC). To assess the potential benefits of such a 2.5-D integration schema this paper compares wire length distributions, obtained for 2-D and 2.5-D implementations of benchmark circuits. In the assessment two newly developed floorplanning and placement tools were used. Significant reductions in both total wirelength and worst-case wirelength was observed for the systems implemented as 2.5-D ICs.

Test generation for current testing (CMOS ICs)

Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout.<<ETX>>

Current signatures: application

Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Application of current signatures in die selection and defect diagnosis is discussed as well.

Built-in current testing

Built-in current (BIC) testing has proven to be useful through a number of IC fabrication experiments. In this paper the experience gained from these experiments is summarized. >