Ronald Ho

High-Speed and Low-Energy Capacitively-Driven On-Chip Wires

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8x over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5x. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7x using a 200 mV swing.

Electronic alignment for proximity communication

This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100/spl mu/m are electrically corrected to within 6.25/spl mu/m. A 0.35/spl mu/m experimental CMOS chip communicates at 1.35Gb/s with a BER /spl les/10/sup -10/.