Ronald J. Lomax

Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates

Results of a two-dimensional finite-element simulation of a GaAs MESFET are presented. The simulation is used to determine the drain current and transconductance as well as the two-dimensional voltage, electron density, and electric-field distributions. It is shown that placement of a compensated doping region in the high electric-field region between gate and drain increases the drain current and transconductance by reducing the velocity-saturation effect. The transconductance and drain conductance of the MESFET in the saturation region of devices having different channel heights are compared with previous analysis.

A finite-difference transmission line matrix method incorporating a nonlinear device model

A variable-mesh combination of the expanded-node transmission line matrix (TLM) and finite-difference-time-domain (FD-TD) methods for solving time-domain electromagnetic problems is described. It retains the physical process of wave propagation and the numerical stability of the former and it has the computational efficiency of the latter. This full-wave finite-difference transmission line matrix (FD-TLM) method utilizes transmission lines of differing impedances to implement a three-dimensional variable mesh, which makes practical the simulation of structures having fine details, such as digital integrated circuits (ICs). Circuit models for lumped resistors, capacitors, diodes, and MESFETs have been developed and included for use in simulating digital and microwave ICs. The validity of the variable mesh implementation is verified by comparing an FD-TLM simulation of a picosecond pulse generator structure with electrooptical measurements, and the validity of the device model implementation is verified by comparing an FD-TLM simulation of a MESFET logic inverter with a SPICE simulation. >

Semiconductor Device Simulation

Two of the numerical methods most widely used in solving the set of partial differential transport equations for holes, electrons, and electric field in semiconductor devices and the various numerical instability phenomena which can be encountered are described in detail. Also presented are approaches, using these methods, to calculate dc static solutions and small-signal solutions, and to simulate devices in voltage-driven, current-driven, and circuit-loaded operation. Sample results are given for each mode of operation for the case of Si avalanche-diode oscillators. The numerical methods and approaches are those developed at our laboratory and sufficient detail is presented to permit the development of similar Fortran codes by others.

The design of a microsupercomputer

A description is given of work to develop a prototype microcomputer that will realize the best of both the supercomputer and the microprocessor traditions. It does so by using GaAs MESFET enhancement/depletion direct-coupled FET logic, a high-speed technology that has good integration density, and state-of-the-art packaging technology to prevent chip crossings from dominating the overall speed of the system. The focus of the research reported is the relationship between hardware implementations and emerging technologies. The MIPS Computer Systems instruction set was implemented to bound the architectural options and to eliminate the need to develop compilers and operating systems. Efforts are concentrated on developing the processor and cache. The resulting system will be a general-purpose computer that runs a conventional Unix environment and supports standard programming languages and networking protocols. The machine will significantly accelerate execution of the existing large base of application software.<<ETX>>

Overview of complementary GaAs technology for high-speed VLSI circuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 /spl mu/W/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.

A microprocessor design project in an introductory VLSI course

An introductory very large scale integration (VLSI) design course has been taught at the University of Michigan (USA) since 1980. In 1990, it was redesigned around a simple 8-bit microprocessor project in the format described in this paper; in 1996, the project was updated to a 16 bit reduced instruction set computer (RISC) processor. The authors describe the course philosophy, content, and the baseline architecture from which class projects begin. The key features of the course are: close coordination of lectures and project activity; prompt and regular feedback on design work; and a schedule which spreads the workload over the full term. In this course, students learn VLSI fundamentals and good design methodology that will be important throughout their careers.

Noise Considerations in Self-Mixing IMPATT-Diode Oscillators for Short-Range Doppler RADAR Applications

The influence of the oscillator noise on the minimum detectable signal of a Doppler RADAR with a self-mixing IMPATT-diode oscillator is evaluated. For very short-range RADARs, it is the AM noise which limits the signal-to-noise ratio and thus the range.

A current-excited large-signal analysis of IMPATT devices and its circuit implications

A large-signal analysis of a Read-type IMPATT diode is carried out with a sinusoidal current as the excitation. The results are compared with analyses that assume a sinusoidal voltage excitation. The large-signal impedance of the diode with current excitation is expressed in closed form. The circuit implications of choosing voltage or current as the excitation are discussed.

Area I/O flip-chip packaging to minimize interconnect length

This paper discusses an approach using area interconnect to achieve high performance for an experimental multichip microprocessor. The described method is being used in the PUMA project at the University of Michigan to design a processor that has a clock speed goal of 1 GHz. The approach relies on the coordinated placement of functional blocks on chips, and the resulting chips on the MCM. The use of area array pads to provide high bandwidth interconnections between the chips, and low inductance power connection to the MCM is also essential. Three stages of MCM development for the project are described.

Multilevel optimization in the design of a high-performance GaAs microcomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer. >