Ronald W. Knepper

Chip Substrate Resistance Modeling Technique for Integrated Circuit Design

With the advent of VLSI and the use of statistical simulation techniques to perform integrated circuit design, modeling of chip substrate resistance is becoming increasingly important to successful chip design. This paper will present a substrate resistance modeling technique which may be applied to the design of both FET and bipolar chips. After briefly presenting the theory behind the technique, we will describe its use in developing a substrate resistance model required for studying a disturb problem encountered with a high-speed array chip. The steps involved in building and simplifying the substrate model will be described. The effect on circuit simulations and noise sensitivity will then be shown.

Dynamic depletion mode: an E/D MOSFET circuit method for improved performance

A new method of designing enhancement/depletion (E/D) MOSFET circuits, involving the dynamic or pulsed use of depletion-mode devices, is described. The method can result in improvements in performance and/or power in the design of memory, logic, and driver circuits. The method is compared with the standard approach to the design of E/D circuits. Several circuits designed by the method have been simulated by use of a numerical circuit analysis program and have been placed on an experimental test chip. Theoretical and experimental results are presented.

A 45 GHz strained-layer SiGe heterojunction bipolar transister fabricated with low temperature epitaxy

Strained-layer Si-SiGe heterojunction bipolar transistors with f/sub t/ as high as 45 GHz are reported. The device structure incorporates a 65 nm SiGe graded base, with a peak Ge concentration of 11%, grown by UHV/CVD (ultrahigh vacuum/chemical vapor deposition) low-temperature epitaxy. The devices show a 10* collector current enhancement and a 30% reduction in base transit time to 2.6 ps.<<ETX>>

Double injection in PπN silicon devices

Abstract Investigation of the d.c. electrical behavior of semiconductor P + πN + double injection devices is presented. The samples studied were fabricated from indium-doped silicon partially compensated by shallow donor impurities and were biased into the double injection (post-breakdown) regime at a temperature of 77°K. A numerical computer solution of the steady-state characteristic has been completed in order to explain the experimental d.c. data. The analysis reveals that electron-hole scattering is largely responsible for the increase in bulk voltage with current. In order to obtain agreement between the numerical solution and the experimental data, the filamentary nature of the double injection current is demonstrated.

Modeling advanced bipolar devices for high performance applications

A bipolar modeling methodology is described which uses a series of 2-D process and device simulation programs and a circuit model generation program each linked together in order to generate equivalent circuit models for numerical circuit simulation. The programs have been used to study process windows and device sensitivities, optimize process and device technology, and generate models for circuit design for IBMs advanced bipolar technology development. The methodology is described using examples of a Si-SiGe n-p-n HBT (heterojunction bipolar transistor) and an integrated VPNP structure. Efforts under development for future bipolar device modeling requirements are briefly described.<<ETX>>

Dynamic depletion mode: An E/D MOSFET circuit method

This paper will describe the dynamic use of depletion-mode devices resulting in improved performance in MOSFET enhancement/depletion circuits. The method - DDM - applies to the design of logic, memory and driver circuits.

Technology CAD at IBM

The IBM suite of TCAD tools for semiconductor process and device modeling is described. The series includes FEDSS for process modeling, FIELDAY for device modeling, FOXi/FIERCE for resistance and capacitance calculation, EXCALIBR and MGP for compact device model generation, and SEMM for soft-error failure probability prediction. Comprising the VATS series of tools, the programs interact through a common database representation, are accessible via a graphics-user-interface WIZARD, and provide for inputs, outputs, and meshing through a number of pre- and post-processor programs.

A comparative device and performance analysis between a Si-Ge epitaxial-base HBT and a Si double-poly I/I BJT npn structure

The device characteristics and performance leverage of a SiGe epitaxial-base heterojunction bipolar transistor (HBT) are compared to those of an advanced Si double-poly ion-implanted (I/I)-base bipolar junction transistor (BJT) npn structure. In addition, a collector-base profile optimization for the SiGe device structure is described. Two-dimensional numerical process and device simulators and a lumped equivalent circuit model generator are used for the comparison along with experimental data. The simulated results show a greater than 3* increase in current gain, a 1.5* increase in the unity-gain cutoff frequency, and a 13% improvement in ECL circuit delay for the SiGe device. The experimental results confirm the device behavior predicted by the simulations.<<ETX>>

Electrical fluctuations in silicon double injection devices

Abstract Studies of the electrical noise behavior of indium-doped silicon P+πN+ double injection devices are reported. The work refers to the double injection portion of the device characteristic at a temperature of 77°K. The noise studied is attributed to fluctuations in the rate of recombination of carriers via the indium centers. From fitting theoretical and experimental results, the carrier lifetime is found to be 2.5 × 10−7 sec and the capture cross-section of neutral indium centers for electrons is determined to be 1.8 × 10−16 cm2.

Modeling the small-emitter effect in polysilicon-emitter transistors

Arsenic shadowing, which is an important consideration for the small-emitter effect in bipolar polysilicon-emitter transistors, was simulated using two-dimensional process and device modeling tools. Results are compared with data for conventional and epi-base polysilicon-emitter technologies. Consideration is also given to other parameters that affect the base current. This analysis shows that the principle features of the arsenic shadowing effect can be modeled and explained by using the simulation tools. These simulations showed that the small-emitter effect was still present in the more advanced epi-base devices.<<ETX>>