Lawrence Wagner

Record RF performance of 45-nm SOI CMOS Technology

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fTs of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fTs are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

SRAM bitline circuits on PD SOI: advantages and concerns

This paper presents a study of sub-0.25-/spl mu/m CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations.

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-μm SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOMT of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is -126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 μW.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability

SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This paper presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime.

A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS

A 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies

We report record RF FET performance in 65 and 90-nm silicon-on-insulator (SOI) CMOS technologies featuring measured gate lengths from 27 to 43 nm and analyze factors contributing to that performance. The effect of layout and geometry optimization as well as channel length scaling is investigated to improve RF performance, namely fT, and fMAX. A peak fT of 330 GHz is measured in a fully-wired 65-nm NFET. A complete de-embedding method to accurately determine RF characteristics of the intrinsic 90-nm SOI NFET results in a peak fT of 290 GHz and an fMAX of 450 GHz

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits

In this paper we show that the ability of SOI NMOS transistors to function as high-bandwidth amplifiers continuously improves as gate length shrinks below 50 nm. fT of 196 GHz is achieved at Lpoly = 47 nm. Neither the transconductance nor the input capacitance reaches a limiting value at Lpoly = 47 nm. The gate sheet resistance, which influences the FET input resistance and high-frequency noise, shows little variation and is an acceptable value (7: /square) in the Lpoly = 55 nm to 77 nm range. We also present four features of an aggressively scaled 0.13-Pm partially-depleted SOI CMOS technology that show its suitability for high-frequency circuit applications: RF noise performance comparable to state-of-the art III-V devices, body-tied SOI FETs that achieve the same low-frequency noise as bulk FETs, a multilevel back-end that allows high-density and high-Q passives, and negligible floating-body-induced jitter in RF circuits. 1. FET scaling

Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process

Power gain (f_MAX) of 350 GHz and cut-off frequency (f_T) of 280 GHz is demonstrated for 36 nm L_poly devices in a 45 nm bulk CMOS process. A record f_T of 350 GHz (intrinsic f_T 425 GHz), without any loss of f_MAX is seen in 28 nm L_poly devices. Combination of advanced lithography and liner stress effect can be leveraged to further boost f_T and f_MAX by 14% with a relaxed pitch device. Comparison with 90 and 65 nm nodes illustrates the impact of scaling and parasitics.