Ronan A.R. van der Zee

Design of Active N-Path Filters

A design methodology for synthesis of active N-path bandpass filters is introduced. Based on this methodology, a 0.1-to-1.2 GHz tunable 6th-order N-path channel-select filter in 65 nm LP CMOS is introduced. It is based on coupling N-path filters with gyrators, achieving a “flat” passband shape and high out-of-band linearity. A Miller compensation method is utilized to considerably improve the passband shape of the filter. The filter has 2.8 dB NF, +25 dB gain, +26 dBm wideband IIP3 ( MHz), an out-of-band 1 dB blocker compression point B1dB,CP of +7 dBm (Δf = +50 MHz) and 59 dB stopband rejection. The analog and digital part of the filter draw 11.7 mA and 3-36 mA from 1.2 V, respectively. The LO leakage to the input port of the filter is ≤-64 dBm at a clock frequency of 1 GHz. The proposed filter only consists of inverters, switches and capacitors and therefore it is friendly with process scaling.

Design and analysis of a high-efficiencyv high-voltage class-D power output stage

The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.

A 0.3-to-1.2GHz tunable 4 th -order switched g m -C bandpass filter with >55dB ultimate rejection and out-of-band IIP3 of +29dBm

The trend towards reconfigurable receivers requires on-chip flexible filters that can replace dedicated, bulky and non-tunable filters (e.g., SAW and BAW [1]). Although BAW filters are compatible with silicon processes, their center frequency is sensitive to thickness variation of the piezoelectric material and the achievable tuneability is limited [1]. Other techniques to make RF on-chip band-pass filters (BPFs) include Q-enhancement, gm-C and N-path. Q-enhancement approach has several disadvantages such as large area due to inductors which do not obey process scaling, limited tuneability and poor dynamic range [2]. Main drawbacks of gm-C filters are the tradeoff between power consumption, quality factor, center frequency and dynamic range and the need for tuning circuitry [3]. Recently there has been renewed interest in the translational impedance conversion of N-path filters [4-6]. Due to the “transparency” of the passive mixer, baseband impedance is translated to frequencies around the clock frequency flo [7]. The interesting features of these filters are their direct tuneability with flo, higher quality factor compared to on-chip CMOS LC filters [2], high linearity and graceful scaling with process.

Performance of chirped-FSK and chirped-PSK in the presence of partial-band interference

To improve interference robustness of wireless communication, spread spectrum techniques are often used. We use the chirp spreading technique along with FSK and PSK binary modulation schemes to obtain interference robust radio communication. The performance of chirped-FSK and chirped-PSK modulation through a white gaussian noise channel is simulated assuming a synchronized clock between transmitter and the receiver. We analyzed and simulated the error probability (BER) of the overall system in the presence of partial band of interference in the channel. The simulated BER is close to the estimated BER and they prove the superior performance of chirp-based modulation in the presence of interference.

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

Piezoelectric actuators are widely used in smart materials for vibration and noise control, precision actuators, etc. [1]. These actuators are largely capacitive and the reactive power applied on them can go to several tens of Watts. Highvoltage, high-power class-D amplifiers [2]-[5] are ideal drivers for such loads, because of their high power efficiency. Preferably, efficiency should be high both at maximum power and at average output power. Obtaining high power efficiency over the full output power range of a class-D amplifier is the main focus of this work.

Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying 2 in 65nm CMOS

The impedance transformation property of passive mixers enables integrated high-Q channel selection at RF with a programmable center frequency through a clock [1,2]. As such, this technique is suitable for addressing both linearity and flexibility requirements in wideband and cognitive radio applications. However, given the typically low resistance level at the RF side of the receiver chain, the RC product necessary for filtering results in large capacitors, and, consequently, large die area that does not scale with technology. In addition, filter rejection at the RF side is limited by the resistance of the switches of the passive mixer. Thus, large switches are typically needed for moderate rejection values (5Ω switches for 16dB rejection [2]), which translates to higher power consumption in the LO buffers. Furthermore, filtering prior to the LNA [1] or eliminating it altogether [3] improves linearity at the expense of noise and switching harmonics being injected directly at the antenna node. Conversely, an LNA first architecture offers an opposite trade-off. This work demonstrates a highly compact design of a direct-conversion receiver with an active feedback frequency translation loop to perform channel selection at the LNA output while simultaneously cancelling its distortion.

26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience

The coexistence of more and more wireless standards in the ISM bands increases the design difficulty of interference-robust receivers (RX), especially for Wireless Sensor Nodes because of their Ultra-Low-Power (ULP) budget.

Choosing optimum noise figure and data rate in wireless sensor network radio transceivers

To reduce the energy consumption in wireless sensor network transceivers, we propose an approach which combines two tradeoffs. The first tradeoff is between the receiver sensitivity and transmitter output power. The second one is the duty cycle and data rate of the transceiver. The combined approach gives us the optimum choice of noise figure and data rate for a given application and transceiver architecture. Considering a typical transceiver architecture and perfectly synchronized system, we show that the energy consumption can indeed be reduced with this approach compared to choosing either data rate or noise figure arbitrarily. Moreover, in case of a wakeup receiver architecture and slot based MAC protocol, applying this method, we show that there is a different combination of optimum data rate and noise figure value for the wakeup receivers to minimize the wakeup energy.

A High-Voltage class-D power amplifier with switching frequency regulation for improved high-efficiency output power range

This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14 μm SOI BCD process, the amplifier achieves 93% efficiency at 45 W output power, > 80% power efficiency down to 4.5 W output power and > 49% efficiency down to 0.45 W output power.

An ultra low energy FSK receiver with in-band interference robustness exploiting a 3-Phase chirped LO

An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal-oxide-semiconductor process. It consumes 219 μW from 1.2 V power supply, while having a sensitivity of -70 dBm for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up to -8 dB signal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.