Rong-Jhe Lyu

Fabrication of High-Performance ZnO Thin-Film Transistors With Submicrometer Channel Length

A method was developed to fabricate ZnO thin-film transistors (TFTs) with submicrometer channel length. In this scheme, mature process techniques are used to form a suspending hardmask bridge on the wafer surface, which enables the subsequent construction of a TFT by the sequential deposition of gate oxide, ZnO channel layer, and Al source/drain contacts. Excellent electrical characteristics were demonstrated by the fabricated ZnO TFTs that show high ON/OFF current ratio , low subthreshold swing (89 mV/decade), and high field-effect mobility (41 cm2/V s). Very small variation in the device characteristics is also demonstrated.

Film profile engineering (FPE): A new concept for manufacturing of short-channel metal oxide TFTs

A film profile engineering (FPE) concept which utilizes the unique features of various deposition tools to tailor and optimize the profile of the deposited films was demonstrated with the fabricated ZnO TFTs. By implementing the PR trimming technique, high performance devices with L <; 100 nm can be readily achieved.

Implementation of Film Profile Engineering in the Fabrication of ZnO Thin-Film Transistors

A novel approach, which can delicately form a desirable film profile for deposited gate oxide, channel, and source/drain contacts of oxide-based thin-film transistors (TFTs) is proposed. To demonstrate the film-profile engineering concept used in this approach, a simple one-mask process was developed for fabricating ZnO TFTs with submicrometer channel length. The fabrication takes advantage of a suspended bridge hanging across the device to tailor the desirable profile of deposited films with proper tools. The fabricated devices show high ON/OFF current ratio (>109), steep subthreshold swing (71-187 mV/decade), and high mobility (21-45 cm2/V·s). Very small variation in device characteristics among the devices with the same channel dimensions is also confirmed.

Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates

By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio (~1010), steep sub-threshold swing (66~108 mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.

High-gain, low-voltage BEOL logic gate inverter built with film profile engineered IGZO transistors

We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable Vth for high-gain BEOL logic gate inverters in a unique film-profile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4-0.8 μm) in a single step, leading to a wide-ranging tunability in Vth of -0.2-+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 μm IGZO TFT and 0.7μm IGZO drive-transistor, respectively, at operation voltage (Vdd) of 9V.

A Film-Profile-Engineered 3-D InGaZnO Inverter Technology With Systematically Tunable Threshold Voltage

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of -2.3-1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.

Novel InGaZnO inverters utilizing film profile engineering

In this study we cleverly employ the film profile engineering (FPE) concept to fabricate amorphous InGaZnO (a-IGZO) thin-film transistor (TFT)-based inverters with a resistor- or transistor-load. In the fabrication the profiles of major thin films in both load and drive devices can be properly tailored with designed channel dimensions and deposition conditions. Although the inverter with a resistor-load is simpler in structure and fabrication, the switching performance is found to be restricted by the passive load component. The performance can be greatly promoted as a depletion-mode transistor-load is used instead. Full-swing operation is demonstrated for the inverter with a voltage gain of 28 recorded at an operation voltage (VDD) of 5 V.

Fabrication of Sub-50nm ZnO thin-film transistors with film profile engineering and laminated hardmask structure

We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.

Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates

Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.

Effects of Ga2O3 deposition power on electrical properties of cosputtered In-Ga-Zn-O semiconductor films and thin-film transistors

In this study, we have successfully fabricated In?Ga?Zn?O (IGZO) thin-film transistors (TFTs) with various Ga2O3 deposition powers prepared using a two radio-frequency (RF) (ceramics targets: In2O3 and Ga2O3) and one direct-current (DC) (metallic target: Zn) magnetron cosputtering system at room temperature. The carrier concentration for the IGZO films decreases to less than 3 ? 1016 cm?3 when the Ga2O3 deposition power is 175 W and Hall mobility decreases from 12.8 cm2 V?1 s?1 and saturates at 4.6 cm2 V?1 s?1 with increasing Ga2O3 deposition power. The increase in the resistivity of the cosputtered films correlates with the decrease in the crystallinity of the InGaZn7O10 phase and the phase transformation from InGaZn7O10 to InGaZn2O5 with increasing Ga2O3 deposition power. With an optimum Ga2O3 deposition power of 150 W, cosputtered IGZO TFTs with a higher, saturated drain current of 4.5 ?A, good saturation mobility, ?sat of 4.92 cm2 V?1 s?1, Ion/Ioff of 109, a low subthreshold swing (SS) of 0.27 V/decade, and RSD of 30 k? have been successfully fabricated.