Bo-Shiuan Shie

Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness

N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 × 1019 cm-3 and the fixed charge density to be around -6 × 1012 cm-2. The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.

Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing

By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO₂/La₂O₃/SiO₂ on Ge n-MOSFETs shows a high gate capacitance density, a small n⁺/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm²/V·s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO₂/Si universal mobility.

Film profile engineering (FPE): A new concept for manufacturing of short-channel metal oxide TFTs

A film profile engineering (FPE) concept which utilizes the unique features of various deposition tools to tailor and optimize the profile of the deposited films was demonstrated with the fabricated ZnO TFTs. By implementing the PR trimming technique, high performance devices with L <; 100 nm can be readily achieved.

Higher κ metal-gate/high-κ/Ge n-MOSFETs with &#60;1 nm EOT using laser annealing

High performance metal-gate/high-κ/Ge n-MOSFETs are reached with low 73 Ω/sq sheet resistance (R<inf>s</inf>), 1.10 ideality factor, 0.95 nm EOT, small 106 mV/dec sub-threshold slope (SS), good 285 cm²/Vs high-field (1 MV/cm) mobility and low 37 mV ΔV<inf>t</inf> PBTI (85°C, 1 hr). This is achieved by using 30-ns laser annealing that leads to 57% higher gate capacitance, better n⁺/p junction and 10X better I<inf>ON</inf>/I<inf>OFF</inf>.

100-nm IGZO Thin-Film Transistors With Film Profile Engineering

100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al2O3 gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>107) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.

Gate-First

To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Ω/sq, a small ideality factor of 1.3, and a large ~10⁵ forward\reverse current in the source-drain n⁺/p junction. The laser-annealed gate-first TaN/La₂O₃/SiO₂/Ge n-MOSFETs showed a high mobility of 603 cm²/Vs and a good mobility of 304 cm²/Vs at a 1.9-nm equivalent oxide thickness.

\hbox{TaN/La}_{2}\hbox{O}_{3}/ \hbox{SiO}_{2}/\hbox{Ge}

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low V<inf>t</inf> of ∼0.15 V are achieved in CMOS by using higher к gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-к/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO<inf>2</inf>/Si universal mobility at an E<inf>eff</inf> of 1 MV/cm.

n-MOSFETs Using Laser Annealing

In this work, we investigate the effectiveness of three organic and inorganic materials as the passivation layers in improving the stability of the a-IGZO devices. Two types of organic materials, FH6400 and Durimide 115A, and inorganic PECVD-SiOX were explored in this work. Because of the effective protection from the diffusion of the gas molecules, especially the oxygen molecules, to the active layer, a-IGZO TFTs with the capping of organic passivation layer show good stability under positive bias stress and also show better stability under light illumination with negative bias stress due to low hydrogen content.

Metal-gate/high-к CMOS scaling from Si to Ge at small EOT

We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.

Stability of InGaZnO thin-film transistors with Durimide passivation

In this paper, high-performance InGaZnO (IGZO) thin-film transistors were fabricated with film-profile-engineering scheme. The impacts of gate dielectric, O₂/Ar ratio during the sputtering of the IGZO, and annealing ambient on the device performance were investigated. It is found that the turn-ON voltage of the device is closely related to the gate dielectric material. For the devices with Al₂O₃ as the gate dielectric, decent performance in terms of high ON/OFF current ratio (>10⁸), extremely steep subthreshold swing (62 mV/decade), and good mobility (19.8 cm²/V·s) is obtained. The influences of O₂/Ar flow ratio are distinct for the devices with Al₂O₃ gate oxide. Significant improvement in the stability of the devices to the environment is achieved with the anneal done in a low-pressure N₂ ambient.