Tiao-Yuan Huang

Novel poly-silicon nanowire field effect transistor for biosensing application

A simple and low-cost method to fabricate poly-silicon nanowire field effect transistor (poly-Si NW FET) for biosensing application was demonstrated. The poly-silicon nanowire (poly-Si NW) channel was fabricated by employing the poly-silicon (poly-Si) sidewall spacer technique, which approach was comparable with current commercial semiconductor process and forsaken expensive E-beam lithography tools. The electronic properties of the poly-Si NW FET in aqueous solution were found to be similar to those of single-crystal silicon nanowire field effect transistors reported in the literature. A model biotin and avidin/streptavidin sensing system was used to demonstrate the biosensing capacity of poly-Si NW FET. The changes of I(D)-V(G) curves were consistent with an n-type FET affected by a nearby negatively (streptavidin) and positively (avidin) charged molecules, respectively. Specific electric changes were observed for streptavidin and avidin sensing when nanowire surface of poly-Si NW FET was modified with biotin and streptavidin at sub pM to nM range could be distinguished. With its excellent electric properties and the potential for mass commercial production, poly-Si NW FET can be a very useful transducer for a variety of biosensing applications.

Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel

In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of >; 107. Moreover, the JL device shows 23 times increase in the on-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products.

Ultrasensitive detection of dopamine using a polysilicon nanowire field-effect transistor

An unprecedented high sensitive sensing of neurotransmitter dopamine at fM level was demonstrated using a poly-crystalline silicon nanowire field-effect transistor (poly-SiNW FET) fabricated by employing a simple and low-cost poly-Si sidewall spacer technique, which was compatible with current commercial semiconductor processes for large-scale standard manufacture.

Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Ge x source/drain

P-channel MOS transistors with raised Si/sub 1-x/Ge/sub x/ and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si/sub 1-x/Ge/sub x/ and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si/sub 1-x/Ge/sub x/ S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R/sub SD/), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R/sub SD/ of devices with Si/sub 1-x/Ge/sub x/ raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g/sub m/) at an effective channel length of 0.16 /spl mu/m. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si/sub 1-x/Ge/sub x/ S/D structure very attractive for future sub-0.1 /spl mu/m p-channel MOS transistors.

Complementary carbon nanotube-gated carbon nanotube thin-film transistor

We introduce, a complementary carbon nanotube (CNT)-gated CNT thin-film field effect transistor (FET). By using two perpendicularly crossed single-wall CNT (SWNT) bundles as the gate and the channel interchangeably, a sub-50nm complementary CNT-FET is demonstrated. It is found that the new CNT-FET shows acceptable FET characteristics by interchanging the roles of the gate and the channel. The unique dual functionality of the device will open up a new possibility and flexibility in the design of future complementary CNT electronic circuits.

Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10/sup 6/ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.

Study on Ge/Si ratio, silicidation, and strain relaxation of high temperature sputtered Co/Si1−xGex structures

As the transistors continue to scale down, the characteristics of high-temperature-sputtered Co/Si1−xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. In this study, we have fabricated Co/Si1−xGex junction using room-temperature and high-temperature (i.e., at 450 °C) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultrahigh vacuum chemical molecular epitaxy. The relative composition of Ge in Ge-rich Si1−zGez precipitate and the solid solution of ternary phase silicide of Co–Si–Ge system were compared between room-temperature and high-temperature sputtered samples. We found that the high-temperature-sputtered samples are more effective in inhibiting lattice relaxation, which would be beneficial for manufacturing metal silicide/Si1−xGex structure devices. Mechanisms were proposed to explain the large difference between the room-temperature and high-temperature sputtered samples. It is believed that the m...

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.

Evaluation of plasma charging damage in ultrathin gate oxides

Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 mm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.

The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with TiN gate electrode

The characteristics of charge trapping during constant voltage stress in an n-type metal–oxide–semiconductor capacitor with HfO2∕SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (ΔVfb) is mainly caused by the trap filling instead of the trap creation [Zafar et al., J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode.