Roxanne Vu

A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.

An Adaptive Body-Biased Clock Generation System in 28nm CMOS

An adaptive forward body biasing technique is implemented in a clock generation and distribution test chip for memory interface applications to enable wide-range and high-fidelity operation. The proposed clock generation system employs a self-body-biased ring voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to adaptively adjust device body voltages over process and temperature variations. Moreover, a differential body-biasing technique incorporated in a duty cycle corrector (DCC) achieves effective correction range with minimal power overhead. The adaptive self-body-biasing technique extends PLL frequency locking range by more than 20 percent while reducing power supply induced jitter (PSIJ) by maximum 25 percent for increased yield and reliable operation.