Stefanos Sidiropoulos

A semidigital dual delay-locked loop

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-/spl mu/m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.

High-speed electrical signaling: overview and limitations

Advances in IC fabrication technology, coupled with aggressive circuit design, have led to exponential growth of IC speed and integration levels. For these improvements to benefit overall system performance, the communication bandwidth between systems and ICs must scale accordingly. Currently, communication links in various applications approach Gbps data rates. These applications include computer-to-peripheral connections, local area networks, memory buses, and multiprocessor interconnection networks. Designers are concerned that these links will soon reach the fundamental limits of electrical signaling. In this article, we examine the limitations of CMOS implementations of highspeed links and show that the links performance should continue to scale with technology. To handle the interconnects finite bandwidth, however requires more sophisticated signaling methods. CMOS circuits, typically slower than circuits implemented in nonmainstream technologies, are particularly attractive for common applications because of their lower cost. The overall system cost is further reduced when signaling components are implemented as macro cells, integrated on the same die with a microprocessor or signal processing block.

A 700-Mb/s/pin CMOS signaling interface using current integrating receivers

A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 /spl mu/m CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10/sup -14/.

A Cmos 500 Mbps/pin Synchronous Point to Point Link Interface

This paper describes the design of a high speed interface for a multiprocessor interconnection network. To achieve higher transfer rates, the interface utilizes a voltage swing of 1 V, a Delay Line PLL and sampling of the data on both edges of the clock. Chips fabricated in a 0.8 pm CMOS technology achieve transfer rates of 700 Mbpdpin operating from a 3.3-V supply. Worst case measured peak-to-peak clock jitter is 260 ps (63 ps RMS). The layout area occupied by the DLL and the associated clock duty cycle adjuster is 460x800 pni2.

A 2 Gb/s/pin CMOS asymmetric serial link

The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25 /spl mu/m CMOS test chip which show that a properly designed asymmetric link can achieve 2 Gb/s using single-ended signalling with a bit-error rate <10/sup -14/.

A 700 Mbps/pin CMOS signalling interface using current integrating receivers

A high speed CMOS signalling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes 1-V push-pull drivers, a Delay Line PLL and sampling of the data on both half-periods of the clock. In order to increase the noise immunity of the reception, current-integrating receivers are used to sample the data in the input pads. Chips fabricated in 0.8-/spl mu/m CMOS technology achieve transfer rates of 740 Mbits/sec/pin operating from a 3.3-V supply with a bit error rate of less than 10/sup -14/.

Current integrating receivers for high speed system interconnects

This paper presents a high speed receiver design that utilizes current integration in order to increase its noise immunity. The integration of current on a capacitor based on the incoming signal voltage effectively averages the incoming signal over its valid time period, therefore filtering out high frequency noise. An experimental design illustrating the concept has been fabricated in a 1.2 /spl mu/m CMOS technology. The receiver dissipates 2.7 mW of power operating from a 5-V supply, achieves error free operation at a clock frequency of 250 MHz, and occupies 60/spl times/450 /spl mu/m/sup 2/ of silicon area.

A speed, power, and supply noise evaluation of ECL driver circuits

Active pull-down circuits can generate less supply noise while having faster circuit delays and dissipating less power than conventional emitter follower circuits. CML or ECDL resistive pullups are quieter but have poor speed-power performance.