Rozana Hussin

Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature

Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300-1000 K for silicon layer thicknesses from 10 nm to 1 mum (and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration

Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.Copyright

Impact of Scaling on Thermal Behavior of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. For the first time the effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated to the hydrodynamic simulation of electrons and holes in a commercial electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of the gate length and silicon layer thickness. The device thermal resistance is increased by more than a factor of 2 due to the scaling of gate length from 180nm to 45nm. Neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two. Thermal resistance of SOI devices with 25nm silicon layer can be up to 8 times larger than that of bulk devices

Thin film In 0.53 Ga 0.47 As Schottky diodes for rectification and photodetection of 28.3 THz radiations

THz and IR detections have generated tremendous interests lately due to their safe non-intrusion nature, and thus have a wide applicability in medical, security, and x imaging. In this work, thin film Au-In0.53Ga0.47As Schottky device are fabricated for 28.3 THz detection. The schematic of the device is shown in Fig. 1, consisting of the thin film Schottky diode and a bowtie antenna. This device structure and design enables dual detection processes; rectification and photodetection. For rectification, a reduced capacitance and a reduced series resistance [1] are achieved by having a small contact area of 140 nm × 140 nm and by using a thin film of 30 nm, which is thinner than the depletion width in the diode [2]. Simultaneously, the thin film allows hot electrons to be generated in both electrodes; resulting in a net photocurrent with the application of DC voltage. The ability to have a simultaneous detection processes result in a relatively high responsivity, which is important for imaging quality.

Novel fabrication method and structure of single crystal thin film In 0.53 Ga 0.47 As Schottky diodes for potential IR applications

Due to their favorable properties, extensive efforts have been done to extend the applications of Schottky diodes into infrared (IR) nonlinear applications. Primarily, efforts have been concentrated in reducing their series resistances and their capacitances in order to increase their cutoff frequencies [1]. Here, we introduce novel single crystal thin film Au-In0.53Ga0.47As Schottky diodes, in which the thickness of the semiconductor is less than the depletion width in the diodes. This leads to a significantly reduced series resistance, which leads to a cutoff frequency of 25 THz. This value is among the highest values reported for Schottky diodes [2]. The diode structure is achieved using a novel film transfer method introduced by our group.

Thin Film In 0.53 Ga 0.47 As Schottky Diodes for 28.3-THz Detection

A thin film Au-In0.53Ga0.47As Schottky diode device has been fabricated for 28.3-THz detection. The design and structure of the diode enable dual detection modes of rectification and photodetection. A small contact area and a thin film results in a reduced capacitance and a reduced series resistance, respectively, which enable nonlinear detection, and, the thin film allows generation of hot carriers in the anode and cathode, which results in a net photocurrent by modulating the barrier heights with a dc voltage. Our experimental results show that the detected current can be explained by the superposition of the two currents, which are theoretically calculated. The maximum responsivity is approximately 0.03 A/W, a relatively high value, which is a direct result of the superposition of the currents. The device structure is achieved by a flip-bond transfer method.

A Process for Transferring and Patterning InAs Quantum Dot Optical Gain Media for HAMR Near Field Optical Sources

We report a process by which a 270 nm layer of optical gain medium is transferred to a dielectric substrate via a flip chip process and patterned into disk structures suitable for microcavity lasers. This process is anticipated to have application to near field transducers for heat assisted magnetic recording (HAMR). Specifically, the gain medium consists of 5 layers of InAs quantum dots embedded in GaAs. The transfer process was accomplished by depositing a series of etch stop layers on the GaAs substrate before the QD gain layers, and then using these etch stop layers in a polishing and etching process to remove the substrate of the gain medium. To support the gain medium during this removal, the GaAs wafer was flipped onto an epoxy layer that had been applied to a glass wafer, where the gain medium layer was eventually left in place and separated from the substrate. This gain medium layer on epoxy was then patterned using photolithography and ion milling. Photoluminescence studies show little effect on the optical properties resulting from the transfer and the patterned devices show optical mode structures consistent with an approach to lasing. However, the epoxy substrate is revealed to be too poor a thermal conductor for optical pumping to reach the lasing threshold. Detailed analysis of the temperature rise upon illumination combined with literature values for the lasing threshold pump levels suggests that substrates with thermal conductivities of around 10 W/m-K are required for the process to yield working lasers.