Rudy Caluwaerts

Post patterning meso porosity creation: a potential solution for pore sealing

The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.

Integration feasibility of porous SiLK* semiconductor dielectric

The feasibility of integrating a SiLK* Semiconductor Dielectric film (*trademark of The Dow Chemical Company) that contains closed pores was studied using a single damascene test vehicle. The study focussed on tool qualification, process set-up and single damascene feasibility to demonstrate technology extendibility. The results indicate that only minor changes have to be made to the process conditions when transitioning from a dense to a porous SiLK* film.

Ultra-low copper baths for sub-35nm copper interconnects

The copper interconnect technology is constrained by the significant current distribution due to the terminal effect for resistive thin seeds. As a result, the current in the wafer center can become insufficient for cathodic protection of thin copper seeds leading to center seed corrosion. To improve the current distribution, the exchange current density can be lowered e.g. by lowering the copper concentration. Our approach is to investigate and develop acid ultra-low copper baths with feature fill capability. For this goal, the optimum additives concentrations were sought and fill studies in 30 nm trenches were performed. In addition, proposing a high acid chemistry that is also compatible with direct plating, would enable the in-situ copper seed formation and filling in one and the same process step for direct plating on non-copper seed.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

Integration of a low permittivity spin-on embedded hardmask for Cu/SiLK resin dual damascene

The feasibility of integrating a low permittivity spin-on hardmask (SoHM) into a Cu dual damascene structure using SiLK* Semiconductor Resin (*trademark of The Dow Chemical Company) has been investigated. The study focussed on the replacement of the embedded etch stop deposited by chemical vapor deposition (CVD) by a low permittivity inorganic film deposited by traditional spin coating. The evaluation was performed using an existing damascene test vehicle. The etch selectivity was evaluated by applying different SoHM thicknesses and etch times. The patterning chemistry used was O/sub 2//N/sub 2/ based, in a high density TCP etch tool. The electrical data collected indicated no significant yield difference when using an embedded SoHM. The integrated k value of the SoHM film is 3.2, as compared to /spl sim/4.0 for SiO/sub 2/ films.

Reliability Characterization of Different Pore Sealing Techniques on Porous Silk Dielectric Films

As device dimensions scale down, the back-end-of-line dimensions scale down as well, which results in an increasing resistance-capacitance delay of the interconnect. In order to compensate for the increase in the capacitance part, porous low-k dielectrics have been introduced in copper interconnect technology. Due to the highly interconnected pore structure of most porous low-k materials, liquid and/or gaseous species fill the pores of the matrix during integration steps. In addition, pores give rise to surface roughness at the top-interface and at the sidewall after etch, which makes it difficult to deposit a thin, continuous barrier in narrow trenches embedded in porous low-k dielectrics. All of the above makes pore sealing a prerequisite for reliable porous low-k integration (Guedj et al., 2004). Different pore sealing techniques are under investigation. In the case of low-k materials in which the porosity is created using a porogen, the porosity creation could also be shifted to a later phase of the integration scheme; either after low-k etch (Caluwaerts et al., 2003) or after metal CMP (Fayole et al., 2004; Jousseaume et al., 2005), which is referred to as post-etch-burn-out (PEBO) and post-CMP-burn-out (PCBO), respectively. It has been demonstrated previously, that the dielectric reliability could be improved considerably by these kinds of pore sealing techniques (Tokei et al., 2004). In this paper, both integration approaches are compared for porous SiLKtrade dielectric resin (k=2.2) from The Dow Chemical Company and the effect of both integration approaches on the interline capacitance, the dielectric reliability and electromigration are investigated and discussed in more detail