Gerald Beyer

Characterization of Cu surface cleaning by hydrogen plasma

When a Cu surface is exposed to a clean room ambient, a surface layer containing Cu2O, CuO, Cu(OH)2, and CuCO3 is formed. Thermal treatment in a vacuum combined with hydrogen plasma can remove this layer. Water and carbon dioxide desorb during the thermal treatment and the hydrogen plasma reduces the remaining Cu oxide. Ellipsometric, x-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectroscopy analyses indicate that the mechanism of interaction of the H2 plasma with this layer depends on temperature. When the temperature is below 150 °C, H2 plasma cannot completely reduce Cu oxide. Hydrogen diffuses through the oxide and hydrogenation of the Cu layer is observed. The hydrogenated Cu surface has a higher resistance than a nontreated Cu layer. The hydrogen plasma efficiently cleans the Cu surface when the substrate temperature is higher than 150 °C. In this case, hydrogen atoms have enough activation energy to reduce Cu oxide and adsorbed water forms as a byproduct of Cu oxide reduction. When the wafer temperature is higher than 350 °C, the interaction of the Cu film with hydrogen and residual oxygen is observed.When a Cu surface is exposed to a clean room ambient, a surface layer containing Cu2O, CuO, Cu(OH)2, and CuCO3 is formed. Thermal treatment in a vacuum combined with hydrogen plasma can remove this layer. Water and carbon dioxide desorb during the thermal treatment and the hydrogen plasma reduces the remaining Cu oxide. Ellipsometric, x-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectroscopy analyses indicate that the mechanism of interaction of the H2 plasma with this layer depends on temperature. When the temperature is below 150 °C, H2 plasma cannot completely reduce Cu oxide. Hydrogen diffuses through the oxide and hydrogenation of the Cu layer is observed. The hydrogenated Cu surface has a higher resistance than a nontreated Cu layer. The hydrogen plasma efficiently cleans the Cu surface when the substrate temperature is higher than 150 °C. In this case, hydrogen atoms have enough activation energy to reduce Cu oxide and adsorbed water forms as a byproduct of Cu oxide reduc...

Two-step room temperature grain growth in electroplated copper

Electroplated copper exhibits some surprising changes at room temperature in sheet resistance, stress, and microstructure. This behavior, now known as self-annealing, is shown here to be intimately linked to the composition of the plating bath and the resulting incorporation of organic additives in the Cu layer. Their addition is a necessary condition for self-annealing to occur, but slows down the process for higher concentrations. The phenomenon also depends critically on film thickness, showing an accelerated transformation when film thickness increases. This dependence is explained in terms of a very rapid primary crystallization from the top surface down just after deposition, followed by a slower lateral recrystallization producing large secondary grains. The stress and sheet resistance during recrystallization are identified as two noncorrelated variables.

Growth mechanism and continuity of atomic layer deposited TiN films on thermal SiO2

In atomic layer deposition (ALD), film thickness control by counting the number of deposition sequences is poor in the initial, nonlinear growth region. We studied the growth of TiN films formed by sequentially controlled reaction of TiCl4 and NH3 on thermal SiO2 during the transient, nonlinear period. Using low-energy ion scattering and Rutherford backscattering spectroscopy analysis, we have found that a three-dimensional growth of islands characterizes the ALD TiN growth on SiO2. Growth at different temperatures (350 °C and 400 °C) affects the extent of the transient region and the rapid closure of the film. At 400 °C, a reduced growth inhibition and an earlier start of three-dimensional growth of islands results in film closure at about 100 cycles, corresponding to a TiN thickness of 24±3 A. At 350 °C the minimum thickness at which the TiN layer becomes continuous is 34±3 A, deposited with 150 cycles.

The Removal of Copper Oxides by Ethyl Alcohol Monitored In Situ by Spectroscopic Ellipsometry

As an interconnect material, copper has the disadvantage of not forming self-limiting oxides, which can negatively affect device performance and reliability. Undesired oxide layers need to be removed by in situ cleaning, before the copper is subjected to subsequent depositions. We have used ethyl alcohol (C 2 H 5 OH) as a vapor phase reducing agent to remove copper oxides formed on electroplated copper films upon exposure to the ambient. Spectroscopic ellipsometry has been used to monitor the reduction process in situ. Ex situ characterization using X-ray photoelectron spectroscopy and atomic force microscopy support in situ measurements. While oxide removal can be achieved at temperatures as low as 130°C, independent of oxide layer thickness and composition, it occurred more efficiently at 200°C, showing compatibility with the low temperature (<400°C) processing requirements of low dielectric constant materials. The initial reaction involves the reduction of Cu 2+ to Cu + species followed by a second phase consisting of Cu + conversion to elemental copper, producing a clean metal surface. Reduction of Cu 2+ to Cu + species is the rate-limiting step as evidenced by enhanced sensitivity to the reaction temperature.

Direct observation of the 1/E dependence of time dependent dielectric breakdown in the presence of copper

Time dependent dielectric breakdown (TDDB) lifetime model study has been performed on a metal-insulator-semiconductor capacitor structure with copper directly deposited on silicon dioxide without a barrier material. The structure generates a low electric field acceleration of time-to-failure, which makes it possible to measure TDDB over a wide range of electric fields from 3.5 to 10 MV/cm and experimentally validate TDDB lifetime model without any assumption and data extrapolation. The experimental results are in good agreement with the so called 1/E model and do not support the E, √E, or power-law model.

Geometry Effect on Impurity Incorporation and Grain Growth in Narrow Copper Lines

Knowledge of the geometry effect on impurity incorporation and grain growth in narrow lines is important for reducing copper line resistivity. In this paper, we investigate impurity incorporation in narrow lines with time-of-flight secondary ion mass spectroscopy. We also study the influence of linewidth, trench depth, pattern density, and overburden on copper grain growth in reduced dimensions. The concentration of chlorine and carbon is found to increase with decreasing linewidth, while the concentration of sulfur is close to the detection limit. This effect contributes to copper superfilling and is consistent with the curvature-enhanced accelerator coverage model. Copper self-anneal slows down as linewidth decreases, although an opposite trend is observed for lines below a width of about 300 nm. Impurity incorporation and geometric constraint retard copper grain growth in narrow lines, resulting in an inverse relationship between copper line resistivity and geometry. However, copper overburden, which has a much larger grain size, can enhance grain growth in narrow lines depending on the line geometry. Reducing impurities and balancing trench depth and copper overburden can be used to reduce the resistivity of narrow copper lines.

Development of sub-10-nm atomic layer deposition barriers for Cu/low-k interconnects

The development of atomic layer deposition (ALD) barriers with a thickness below 10 nm for copper/low-k dielectric interconnects was reviewed. The CMOS 65-nm technology node, which is presumably the first node, at which ALD barriers will be employed, was taken as a reference. The ALD barrier process will most likely meet the geometrical requirements, i.e. the capability to deposit barrier films in narrow dimensions. In order to establish the compliance of ALD barriers with the thickness requirements, the growth of the ALD layer was investigated. It was shown that the growth of the ALD films proceeds via islands, which are formed in the nucleation step. The thickness, which is necessary to close the surface of the substrate, depends on process conditions and barrier material. It is argued that the minimum barrier thickness should be at least of the same order as the thickness to achieve closure. In the 65-nm technology node barriers have to be compatible with low-k dielectric materials. To achieve growth of ALD barriers on dense low-k materials, surface treatments of the dielectric films have to be implemented. The deposition of ALD films on dielectric materials with an interconnected pore structure results in penetration of the ALD precursors into the pore system and deposition of the barrier inside the dielectric material.

Reliability challenges for copper low-k dielectrics and copper diffusion barriers

Abstract The performance of interconnects containing micro- (pore size smaller than 2 nm) and meso-porous (pore size larger than 2 nm) interlevel dielectrics is influenced by material selection, integration scheme and virtually all fabrication steps. It is generally reported that the reliability margin of the dielectric/barrier/copper system is shrinking. Barrier and dielectric integrity play a most important role in line-to-line leakage and Time Dependent Dielectric Breakdown (TDDB) reliability. TDDB has never been an issue for Cu-SiO2 interconnects, but for sub-100 nm copper/barrier/low-k systems it becomes challenging. When monitoring the integrated dielectric properties early failures can be caused by weak integration interfaces, dielectric damage during the integration, defective diffusion barrier or other non-uniformities related to the damascene process. Recent advances are reviewed along with examples and reference to state of the art.

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

Post patterning meso porosity creation: a potential solution for pore sealing

The creation of meso porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD barriers. The dielectric stack consists of developmental porous SILK (v7) resin (SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SILK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process sequence, which gives rise to large, exposed pores at the sidewall.