Zsolt Tokei

Design Technology co-optimization for N10

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.

Effects of Bias, Pressure and Temperature in Plasma Damage of Ultra Low-k Films

Introduction. One of the most critical challenges during the integration of porous low-k materials in ULSI devices is their degradation during plasma treatments. Removal of the carbon containing hydrophobic groups can occur during strip and cleaning processes when exposed to process radicals. Further moisture adsorption leads to the film degradation. In addition, the “field damage” caused by ion radiation during plasma processing can also be problematic. Although these effects are discussed in many papers [1,2], the dominant factors of plasma damage are still a subject of intensive discussions. It has been shown that O2 plasma cause damage manifested as undesirable chemical modification (carbon depletion), while H2 based plasmas have more complicated behavior. Some authors report no effect in low-k films, others that it enhances the film properties, and others indicate severe damage [2].

Metal stack optimization for low-power and high-density for N7-N5

One of the key challenges while scaling logic down to N7 and N5 is the requirement of self-aligned multiple patterning for the metal stack. This comes with a large cost of the backend cost and therefore a careful stack optimization is required. Various layers in the stack have different purposes and therefore their choice of pitch and number of layers is critical. Furthermore, when in ultra scaled dimensions of N7 or N5, the number of patterning options are also much larger ranging from multiple LE, EUV to SADP/SAQP. The right choice of these are also needed patterning techniques that use a full grating of wires like SADP/SAQP techniques introduce high level of metal dummies into the design. This implies a large capacitance penalty to the design therefore having large performance and power penalties. This is often mitigated with extra masking strategies. This paper discusses a holistic view of metal stack optimization from standard cell level all the way to routing and the corresponding trade-off that exist for this space.

Impact of process variability on BEOL TDDB lifetime model assessment

We investigate the impact of process variability on BEOL TDDB lifetime model assessment. The change in functional form of TDDB lifetime plots due to line-to-line variability and line-edge-roughness has been quantified in the field range in which long term TDDB measurements have been obtained. We found that the Pearson R2, which is used as a measure of linearity of a lifetime plot, did not significantly change due to process variability. Where process variability has a significant effect on TDDB and needs to be taken into account during data analysis, our simulations suggest that it does not have an impact on BEOL TDDB lifetime model assessment. We propose that the conclusions from recent literature reports which point in the direction of a less conservative model compared to the √E-model are valid, although they do not take process variability into account during the data analysis.

Intrinsic reliability of local interconnects for N7 and beyond

The intrinsic Time Dependent Dielectric Breakdown properties of the spacer between gate and first level local interconnects are assessed for dielectrics and spacings compatible with N7 and beyond. The intrinsic reliability properties down to 3nm thickness of standard LPCVD Si3N4- and PECVD Si3N4-films as well as more advanced Al2O3- and low-k CVD SiN-layers have been studied using imecs pcap test vehicle. It turned out that the leakage current of the more advanced films are not worse compared to the more standard layers. Besides, their reliability performance, in terms of Emax, is the same or even slightly better. Down to 3nm thickness, Emax-values higher than 3.5MV/cm were obtained for all dielectrics studied. Fundamental insight in the breakdown processes is obtained by testing a wide thickness range (3-20nm) for the PECVD Si3N4-layer, where higher Emax and QBD were found for the thinner layers, suggesting that less damage is created by electrons when injecting them into thinner films (fluence driven failure mechanism). A difference in leakage and reliability when applying different polarities suggests different mechanisms playing a role when the electrons are injected from the interconnect or from the gate metal. Finally, field simulations at critical locations in the studied structure were used to assess places of higher local field enhancement. We found that at these places, the fields were still lower compared to the Emax-values of the intrinsic films, suggesting that scalability down to 3nm spacer thickness is intrinsically reliable.

Advanced full-automatic inspection of copper interconnects

The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.

Self-aligned block technology: a step toward further scaling

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.

Shaping interconnect technology for an interconnected society

The continuous drive to increase the functionality of electronic products in terms of computational efficiency and versatility requires a broad range of interconnect technologies. This paper presents an overview of advanced CMOS Interconnect technology scaling towards the 10 nm node enabling the increase in 2D computational density. Functional versatility is enabled by 3D interconnection technologies to build heterogeneous Systems-In-Package. The convergence of bio technologies and electronics will bring a new wave of smart energy efficient miniaturized electronic systems capable to sense and respond to humans.

Session 32: Characterization, reliability, and yield - defect characterization and dielectric breakdown

The session starts with a novel characterization technique called trap spectroscopy by charge injection and sensing (TSCIS). The technique allows one to characterize the trap density profile and trap energy level in dielectric materials. In the second paper the chemical nature of the percolation path is studied experimentally using high resolution electron energy loss spectroscopy (EELS). The next paper provides a link between the interface layers and bulk defects using kinetic MC simulations/analytical models and analyzes the impact on the breakdown statistics. In the fourth paper a new gate current random telegraph noise (RTN) measurement method will be presented in an attempt to identify the location of traps generated in high-k and interfacial layers. In the final paper the impact of interfacial layer on the metal/high-k gate stack breakdown is studied