Ruili Wu

A SiGe Envelope-Tracking Power Amplifier With an Integrated CMOS Envelope Modulator for Mobile WiMAX/3GPP LTE Transmitters

This paper presents a SiGe envelope-tracking (ET) cascode power amplifier (PA) with an integrated CMOS envelope modulator for mobile WiMAX and 3GPP long-term evolution (LTE) transmitters (TXs). The entire ET-based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power-added efficiency of 33%/42% at 2.4 GHz for the WiMAX 64 quadrature amplitude modulation (64QAM) and the 3GPP LTE 16 quadrature amplitude modulation, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared to the conventional fixed-supply cascode PA, our ET-based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude spec at close to its P1dB compression without the need of predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35-μm SiGe BiCMOS process on the same die. This study represents an essential integration step toward achieving a fully monolithic large-signal ET-based TX for wideband wireless applications.

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

This paper presents the design insights for the implementation of a fully monolithic radio frequency (RF) power amplifier (PA) using both envelope-tracking (ET) and transistor resizing techniques for long-term evolution (LTE) applications. At the low output power region, some of the power cells in the PA can be disabled to further save power consumption, thus enhancing the efficiency from a traditional ET-PA. Our ET-PA system is first realized with a two-chip solution, consisting of a high voltage envelope modulator fabricated in a 0.35 μm Bipolar-CMOS-DMOS (BCD) technology, and a differential cascode PA in a 0.35 μm SiGe BiCMOS technology. This two-chip solution of the ET-PA is to showcase the effective efficiency enhancement of using the transistor resizing method. In the second design, a CMOS envelope modulator is integrated with the cascode PA on the same die in the 0.35 μm SiGe BiCMOS technology. Some insights are demonstrated regarding the optimization of the envelope modulator specific to our cascode PA for LTE broadband signals, where the finite bandwidth and the switching frequency of the envelope modulator are considered for achieving the minimal error-vector magnitude (EVM) and spurious noise. The fully monolithic BiCMOS ET-PA reaches the maximum linear output power (Pout) of 24 dBm and 23.4 dBm with overall power-added-efficiency (PAE) of 41% and 38% for the LTE 16QAM 5 MHz and 10 MHz signals at 1.9 GHz, respectively, without needing predistortion. At the low power mode of our ET-PA, an additional PAE enhancement of 4% is obtained at Pout of 16-20 dBm by disabling some of the PA power cells. Our fully monolithic ET-PA satisfies the LTE 16QAM linearity specs with high efficiency.

High-Efficiency Silicon-Based Envelope-Tracking Power Amplifier Design With Envelope Shaping for Broadband Wireless Applications

This paper presents a highly efficient silicon-based envelope-tracking power amplifier (ET-PA) for broadband wireless applications. A pseudo-differential power amplifier (PA) is designed using two integrated SiGe power cells fabricated in a 0.35- μm SiGe BiCMOS technology with through-silicon-via (TSV). In the continuous-wave (CW) measurement, the PA achieves a saturated output power (POUT) of around 2 W with power-added efficiency (PAE) above 65% across the bandwidth of 0.7-1.0 GHz. To optimize the ET-PA system performance, several envelope shaping methods such as dc shifting, envelope scaling, envelope clipping, and envelope attenuation at back-off have been investigated carefully. A highly efficient monolithic CMOS envelope modulator (EM) integrated circuit (IC) is designed in a 0.35- μm bipolar-CMOS-DMOS (BCD) process to mate with our SiGe PA. With the LTE 16 QAM 5/10/20-MHz input signals, our ET-PA system achieves around 28 dBm linear POUT, passing the stringent LTE linearity specs such as the spectrum emission mask with an average composite system PAE of 42.3%/41.1%/40.2%, respectively. No predistortion is applied in this work.

A Fully Monolithic BiCMOS Envelope-Tracking Power Amplifier With On-Chip Transformer for Broadband Wireless Applications

This letter presents a power-combined BiCMOS power amplifier (PA) system using envelope-tracking (ET) to serve as a fully monolithic solution for high peak-to-average ratio (PAR) broadband signals. The system consists of two cascode unit PAs combined by an on-chip transformer and modulated by a single envelope modulator. Without needing predistortion, the maximum linear output power of 24.6 dBm/23.8 dBm/23.2 dBm can be achieved with overall power-added-efficiency (PAE) of 26%/24%/22.5% for the LTE 16QAM 5 MHz/LTE 16QAM 10 MHz/WiMAX 64QAM 5 MHz signals at 1.9 GHz. The proposed power-combined ET-PA is fabricated in the TSMC 0.35 μm SiGe BiCMOS technology.

A highly efficient watt-level SiGe BiCMOS power amplifier with envelope tracking for LTE applications

In this paper, a pseudo-differential power amplifier (PA) is designed using two SiGe power cells fabricated in the 0.35-μm IBM 5PAe SiGe BiCMOS technology with through-wafer-vias (TWVs). In the continuous wave (CW) measurement, the PA achieves a 2-watt level saturated POUT with power-added-efficiency (PAE) above 65% across the bandwidth of 0.7-1 GHz. The envelope tracking (ET) technique is then applied to the PA for enhanced efficiency using the LTE 16QAM signals with a peak-to-average-ratio (PAR) of 7.5 dB. Beside a conventional single buck converter based envelope modulator (SBEM), a dual buck converter based envelope modulator (DBEM) is also designed for higher power drivability. Measurement shows the ET-PA systems can transmit linear POUT of 25/24 dBm with system PAE of 40%/32% at 750 MHz for LTE 16QAM 5/20 MHz signals.

Design trade-offs for single-ended vs. differential Class-E SiGe bipolar power amplifiers with through-wafer-vias at 2.4GHz

In this paper, we examine the design trade-offs of several Watt-level 2-stage single-ended and differential Class-E SiGe power amplifiers (PAs) at 2.4GHz. The circuits are designed in a 0.35µm IBM 5PAe SiGe BiCMOS technology with through-wafer-via (TWV) technology to minimize the detrimental parasitic ground inductance. SPICE simulations show that a 2-stage single-ended cascode PA can achieve high power gain of 30 dB with output power Psat/P1dB =29.5/27dBm, peak power-added efficiency (PAE) of 51%, with −30dBc 2nd order harmonics and −44dBc 3rd order harmonics for CW input. Using a low-loss output balun, a differential PA can deliver higher output power than its single-ended counterpart; however, our proposed TWV-aided single-ended PA exhibits much better PAE with a smaller die area than its differential PA counterpart. The advantage of the differential PA will diminish quickly when the loss of the required output balun reaches above 1dB.

A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiency

In this paper, a monolithic 2-stage differential power amplifier (PA) is designed and fabricated in the 0.35 μm IBM 5PAe SiGe BiCMOS technology where the through-wafer-vias (TWVs) are available. A cascode topology is adopted to relieve the voltage stress for the power stage transistors. All components are integrated on-chip for the PA except the input/output baluns. The envelope tracking (ET) technique is applied to this 2-stage PA to enhance the PAE and linearity for high power-to-average-ratio (PAR) Long-Term-Evolution (LTE) signals. The ET-based PA system achieves a linear output power of 20.4 dBm with a gain of 30.5 dB and an overall system PAE of 22%, using an LTE 16QAM 5 MHz signal with ~7.5 dB PAR at 1.85 GHz. Compared to the 2-stage PA operating with fixed voltage supplies, the ET-based PA system improves the linear output power by 3.2 dB and its system PAE by over 10%.

Design of monolithic silicon-based envelope-tracking power amplifiers for broadband wireless applications

This paper presents some design insights on achieving a fully monolithic silicon-based radio frequency (RF) power amplifier (PA) using the envelope-tracking (ET) techniques for low-power broadband wireless applications. We will show that from our design experience, the highly integrated BiCMOS envelope-tracking power amplifier (ET-PA) system provides considerable efficiency-linearity enhancement, and works well with impressive power-saving for broadband 3G/4G cellular signals of high peak-to-average ratio (PAR). We will also demonstrate that further performance improvement of the fully monolithic BiCMOS ET-PA can be accomplished by: (1) combination of ET and transistor resizing techniques at the low output power regions; and (2) utilizing the ET technique with on-chip transformer power-combined SiGe PA for higher linear output power. For example, the fully monolithic BiCMOS ET-PA reaches the maximum linear output power (Pout) of 22.3/24.3 dBm with the overall power-added-efficiency (PAE) of 33%/42% at 2.4 GHz for the WiMAX 64QAM and the 3GPP LTE 16QAM modulations, respectively, without needing predistortion. Additionally, it can exhibit a highly efficient broadband characteristic for potential multi-band applications.

A highly-efficient RF polar transmitter using SiGe power amplifier and CMOS envelope-tracking amplifier for mobile WiMAX

This paper presents a large-signal envelope-tracking (ET) polar transmitter (TX) system with a monolithic cascode SiGe power amplifier (PA) for mobile WiMAX applications. The envelope amplifiers are designed in the TSMC 0.35µm SiGe BiCMOS technology and also with discrete components for comparisons. The entire polar TX system using the discrete envelope amplifier in measurement achieves the power-added efficiency (PAE) of 30% at the average output power of 18 dBm with the EVM of 5% for WiMAX 64QAM 10 MHz signal. The RF/analog/digital co-simulations of the entire polar TX system with the integrated CMOS envelope amplifier show similar linearity and efficiency performances when compared with the measurement results. Both the simulation and measurement data suggests our polar TX design achieves the highest PAE among the state-of-the-art Si-based OFDM polar TX systems reported in the literature.

A highly-efficient BiCMOS cascode Class-E power amplifier using both envelope-tracking and transistor resizing for LTE-like applications

This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-added-efficiency (PAE) of 38% at its 1 dB compression point (P1dB) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4–5% at ≥4 dB back-off from its P1dB. This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions.