Yen-Ting Liu

A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Ultrathin Oriented BiFeO3 Films from Deposition of Atomic Layers with Greatly Improved Leakage and Ferroelectric Properties

Highly (001)-oriented BiFeO3 ultrathin films of total thickness of less than 10 nm were deposited on Si(001) substrates via deposition of atomic layers (ALD) with a LaNiO3 buffer. A radio-frequency (RF)-sputtered sample of the same thickness was prepared for comparison. The ALD combined with interrupted flow and an exchange reaction between Bi and Fe precursors provides a superior method to grow ternary compounds. According to X-ray diffraction, upon deposition at a temperature of less than 550 °C, the only phase in the film was BiFeO3. Anomalous fine structure from synchrotron X-ray diffraction certified the valence bonding through the BiFeO3 (001) diffraction signal. The stoichiometric ratio of BiFeO3 obtained from X-ray photoelectron spectroscopy indicated that ALD has a proportion much improved over the RF preparation, and this is also in agreement with the results for diffraction anomalous fine structure. The use of high-resolution transmission electron and atomic force microscopes showed that the layer structure and morphology from ALD presented a satisfactory coverage, more conformal than that with the RF method. The BiFeO3 thin film deposited with ALD shows excellent leakage, improved at least 1000 times with respect to the RF preparation, making this method suitable for the fabrication of ferroelectric random-access memory devices. From the hysteresis loop, the largest remanent polarization was observed as 2Pr = 2.0 μC cm(-2).

Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN–Alumina–Nitride–Vacuum–Silicon Structure

High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.

A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering

In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC (hot carrier) and NBT (negative bias temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (110)/(100) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/( 100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices

P‐7: Improving Electrical Performance of the Scaled Low‐Temperature Poly‐Si Thin Film Transistors Using Vacuum Encapsulation Technique

A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-Situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-Situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.