Weibo Hu

A SiGe Envelope-Tracking Power Amplifier With an Integrated CMOS Envelope Modulator for Mobile WiMAX/3GPP LTE Transmitters

This paper presents a SiGe envelope-tracking (ET) cascode power amplifier (PA) with an integrated CMOS envelope modulator for mobile WiMAX and 3GPP long-term evolution (LTE) transmitters (TXs). The entire ET-based RF PA system delivers the linear output power of 22.3/24.3 dBm with the overall power-added efficiency of 33%/42% at 2.4 GHz for the WiMAX 64 quadrature amplitude modulation (64QAM) and the 3GPP LTE 16 quadrature amplitude modulation, respectively. Additionally, it exhibits a highly efficient broadband characteristic for multiband applications. Compared to the conventional fixed-supply cascode PA, our ET-based cascode PA meets the WiMAX/LTE spectral mask and error vector magnitude spec at close to its P1dB compression without the need of predistortion. The SiGe PA and the CMOS envelope modulator are both designed and fabricated in the TSMC 0.35-μm SiGe BiCMOS process on the same die. This study represents an essential integration step toward achieving a fully monolithic large-signal ET-based TX for wideband wireless applications.

An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method

An 8-bit single-ended ultra-low-power successive approximation register (SAR) ADC with a novel DAC switching method is designed and fabricated in a 0.35-μm BCD (bipolar-CMOS-DMOS) technology. The switching method uses VR/2, rather than VR, as the only reference voltage to digitize the input signals with the amplitude range of (0, VR). The scheme is also compared with other switching methods in MATLAB. Compared with the conventional switching method, the proposed design reduces the average power consumption in the DAC during digitizing by 87.5%. Measurement results show that at the power supply of 1.4 V and the reference voltage of 1 V and with the sampling rate of 2 kS/s, the ADC can digitize the input signal with a full-scale range of 2 V, resulting in a signal-to-noise-and-distortion ratio (SNDR) of 48.2 dB at the frequencies larger than its Nyquist bandwidth (1 kHz). It consumes 101 nW and reaches a figure of merit of 227 fJ/(conversion-step). The ADC is targeted to be used as part of the ultra-lowpower analog front-end circuit of an implantable cardioverter defibrillator (ICD).

An ultralow-power CMOS transconductor design with wide input linear range for biomedical applications

This paper presents an ultralow-power CMOS linear transconductor design operating in weak inversion for low frequency gm-C filter design for potential biomedical applications, where the transconductance should be low to reduce the capacitor size, and linear to minimize distortion. Bulk-driven and degeneration techniques are used, and we have adopted this Gm cell as a linear source degeneration resistor to achieve a 91% reduction in the transconductance value. In addition, a fourth-order Butterworth bandpass filter was designed in a proprietary 0.35-μm BCD (bipolar-CMOS-DMOS) process by Texas Instruments (TI). The SPICE simulation results indicate that the total harmonic distortion is greatly reduced to less than -71 dB at an input of 100 mV. The power consumption is only 750 nW at a 3-V supply voltage.

An ultra-low power interface CMOS IC design for biosensor applications

This paper presents a design example of an ultra-low power single-channel analog front-end (AFE) integrated circuits (IC) and system for biomedical sensing applications. The 0.18-μm CMOS AFE IC design includes a low noise instrumentation amplifier (INA), a low-pass filter (LPF), a variable gain amplifier (VGA), and a successive approximation register (SAR) analog-to-digital converter (ADC). The AFE IC architecture is analyzed on the system level to minimize total power consumption with high integration and optimized for an ECG sensing system. SPICE simulations of the AFE IC channel validate the ultra-low power IC design methodology for heartbeat detection with less than 1 μA/channel.

Design of monolithic silicon-based envelope-tracking power amplifiers for broadband wireless applications

This paper presents some design insights on achieving a fully monolithic silicon-based radio frequency (RF) power amplifier (PA) using the envelope-tracking (ET) techniques for low-power broadband wireless applications. We will show that from our design experience, the highly integrated BiCMOS envelope-tracking power amplifier (ET-PA) system provides considerable efficiency-linearity enhancement, and works well with impressive power-saving for broadband 3G/4G cellular signals of high peak-to-average ratio (PAR). We will also demonstrate that further performance improvement of the fully monolithic BiCMOS ET-PA can be accomplished by: (1) combination of ET and transistor resizing techniques at the low output power regions; and (2) utilizing the ET technique with on-chip transformer power-combined SiGe PA for higher linear output power. For example, the fully monolithic BiCMOS ET-PA reaches the maximum linear output power (Pout) of 22.3/24.3 dBm with the overall power-added-efficiency (PAE) of 33%/42% at 2.4 GHz for the WiMAX 64QAM and the 3GPP LTE 16QAM modulations, respectively, without needing predistortion. Additionally, it can exhibit a highly efficient broadband characteristic for potential multi-band applications.

CMOS Envelope Tracking amplifier IC design for high-efficiency RF polar transmitters

A monolithic polar transmitter (TX) subsystem that includes a CMOS Envelope Tracking (ET) amplifier and a RF SiGe BiCMOS power amplifier (PA) for mobile WiMAX applications is presented. Several versions of the ET amplifiers are designed and their power consumption and bandwidth considerations are discussed. Consequently, the entire polar TX system performances and design trade-offs are presented and compared against different ET amplifiers design. The IC occupies a total area of 1×1.4 mm2 and is being fabricated in a TSMC 0.35µm SiGe BiCMOS process. RF/Analog/Digital system co-simulation indicates that the overall ET-based polar TX system exhibits 30% Power-Added-Efficiency (PAE) and 4.6% Error Vector Magnitude (EVM) at 19dBm PA output power and passes the stringent output spectral mask for a 10 MHz mobile WiMAX 64QAM signal with ∼10dB Peak-to-Average-Power Ratio (PAR).

A SiGe BiCMOS cascode power amplifier with monolithic SOI envelope modulators for high-efficiency envelope tracking

In this paper, a fully differential cascode power amplifier (PA) is designed and fabricated using a 0.35-μm SiGe BiCMOS process. In the continuous wave (CW) measurement, the PA achieves a saturated power (PSAT) of 24.8 dBm at 3.3 V with power-added-efficiency (PAE) above 50% at 2.3 GHz. Two monolithic envelope modulators (EMs) are designed in a 0.18-μm SOI CMOS technology using a switching buck converter stage with two different linear amplifier topologies: a low-dropout (LDO) regulator vs. a conventional class AB Op-Amp. The envelope tracking PA (ET-PA) systems are measured for maximum linear POUT and efficiency with corresponding design trade-offs discussed. The conventional class AB Op-Amp based EM proved better combined efficiency /linearity at 20 dBm POUT with 30% PAE using an LTE 16QAM 5 MHz signal for our assessment.