Russell Radke

A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order /spl Sigma//spl Delta/ digital-to-analog converter (DAC) with 64/spl times/ oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The /spl Sigma//spl Delta/ DAC is fabricated in a 2-/spl mu/m CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA.

A 0.18-

An Li-ion battery charger based on a charge-control buck regulator operating at 2.2 MHz is implemented in 180 nm CMOS technology. The novelty of the proposed charge-control converter consists of regulating the average output current by only sensing a portion of the inductor current and using an adaptive reference voltage. By adopting this approach, the charger average output current is set to a constant value of 900 mA regardless of the battery voltage variation. In constant-voltage (CV) mode, a feedback loop is established in addition to the preexisting current control loop, preserving the smoothness of the output voltage at the transition from constant-current (CC) to CV mode. A small-signal model has been developed to analyze the system stability and subharmonic oscillations at low current levels. Transistor-level simulations of the proposed switching charger are presented. The output voltage ranges from 2.1 to 4.2 V, and the power efficiency at 900 mA has been measured to be 86% for an input voltage of 10 V. The accuracy of the output current using the proposed sensing technique is 9.4% at 10 V.

\mu{\hbox {m}}

In this paper, a novel multimode crystal oscillator approach is proposed for a Power Management Unit (PMU). It consists of a digitally controlled Automatic Gain Control (AGC) loop allowing multiple power modes to meet the systems low phase noise and power consumption requirements. A new technique with a programmable switched capacitor array controlled by a counter is presented preserving the integrity of the clock during the mode transition. A 32.768 kHz crystal oscillator using the proposed idea was fabricated in a 0.18 μm CMOS technology. Measurement results show that it achieves phase noise of -120 dBc/Hz at 1 kHz offset in normal operating mode and only consumes 860nA current off 3.3V backup battery in RTC-only (low-power) mode including all the digital supporting circuitry. It also shows the seamless transition between the operating modes.