Aria Eshraghi

A CMOS transconductor with 80-dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V/sub pp/ differential inputs up to 10 MHz. The combination of resistors at the input and negative feedback around the operational transconductance amplifier (OTA) allows this transconductor to accommodate a differential input swing of 4 V with a 3.3-V supply. The total harmonic distortion (THD) of the transconductor is -77 dB at 10 MHz for a 3.6-V/sub pp/ differential input and third-order intermodulation spurs measure less than -79 dBe for 1.8-V/sub pp/ differential inputs at 1 MHz. The transconductance core dissipates 10.56 mW from a 3.3-V supply and occupies 0.4 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.

A comparative analysis of parallel delta-sigma ADC architectures

Parallelism can be used to increase the conversion bandwidth of delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADCs). Time-interleaved, parallel /spl Delta//spl Sigma/, and frequency-band-decomposition ADCs are three parallel architectures that are shown to be explained using the same underlying theory. This common structure is then used to explore the design tradeoffs among these architectures. It is shown that the frequency-band-decomposition ADC is insensitive to channel mismatches but it is the most complex to design. The Hadamard modulated parallel /spl Delta//spl Sigma/ ADC provides the best performance (without considering nonidealities) but requires large digital filters. Finally, a randomization technique is described that can be used with parallel /spl Delta//spl Sigma/ architectures to spread out the tonal energy due to channel mismatches over the frequency spectrum.

A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order /spl Sigma//spl Delta/ digital-to-analog converter (DAC) with 64/spl times/ oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The /spl Sigma//spl Delta/ DAC is fabricated in a 2-/spl mu/m CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA.

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators.

Design of a new squaring function for the Viterbi algorithm

An approximate squaring method has been developed for the Viterbi algorithm that is faster and more area efficient than conventional exact squaring methods and table look-up. Using Monte-Carlo simulations, it is shown here that the performance of the Viterbi algorithm is not degraded using this approximation. The circuit performance is verified by implementing a 7-b approximate squaring function in a 2-/spl mu/m CMOS process. It operates at a maximum speed of 20 MHz, consumes 95 pW/Hz of power, and occupies an active area of 380 /spl mu/m/spl times/650 /spl mu/m. >

Calibration of parallel /spl Delta//spl Sigma/ ADCs

A method of calibrating the gain and offset of each channel in parallel /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) is presented. It uses a digital /spl Delta//spl Sigma/ modulator to perform fast and simple offline calibration. Simulations performed on the converter show greater than 30-dB reduction in unwanted tones when this calibration algorithm is used on an eight-channel second-order time-interleaved parallel converter with a 1% gain mismatch and 1-mV offset mismatch. The calibration method is general and can be used with any parallel /spl Delta//spl Sigma/ ADC including time-interleaved- and Hadamard-modulation-based architectures.

A spurious-free delta-sigma DAC using rotated data weighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order three-bit delta-sigma DAC with 64 times oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit linear converter. The 2 /spl mu/m CMOS prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion even for DAC component mismatches as large as 15%.

An area efficient time-interleaved parallel delta-sigma A/D converter

Using a time-interleaved A/D converter is one method of obtaining a Nyquist-rate A/D converter from delta-sigma (/spl Delta//spl Sigma/) A/D converters. In this paper, it is shown that the performance of the time-interleaved /spl Delta//spl Sigma/ A/D converter is as good as other forms of parallel /spl Delta//spl Sigma/ A/D converters. The issue associated with the gain mismatch among the channels is addressed with a proposed solution to circumvent the channel matching problem.

Delta-sigma A/D converters: the next generation

Delta-sigma A/D converters are well suited for applications requiring high resolution in a relatively low frequency bandwidth. As the technology continues to mature, the next generation of delta-sigma A/D converters will be exploited for applications requiring both high resolution and high speed. This paper describe three approaches to extending the useful bandwidth of the delta-sigma A/D converter. They include the use of multibit quantization with feedforward digital compensation, multibit quantization with feedback dynamic element matching and the use of parallelism.

A comparison of three parallel /spl Delta//spl Sigma/ A/D converters

One way to increase the conversion bandwidth of the Delta-Sigma (/spl Delta//spl Sigma/) A/D converter is to use parallelism. The three main types of parallel /spl Delta//spl Sigma/ A/D converter which are practical for implementation are the time-interleaved, the parallel /spl Delta//spl Sigma/ (/spl Pi//spl Delta//spl Sigma/), and the frequency band decomposition A/D converters. In this paper, it is shown that the operation of all three approaches can be explained using the same underlying theory. This common structure is then used to explore the design tradeoffs among these architectures.