Ryo Nagai

AC hot-carrier effects in scaled MOS devices

AC hot-carrier effects with complete precautions against the wiring inductance noises were investigated to get a universal guideline from the viewpoints of AC conditions and device structures (single drain (SD), LDD, and GOLD). Pulse-induced-noises due to the wiring inductance of measurement systems screens intrinsic AC effects. After precautions against noises, AC hot-carrier degradation can be estimated in LDD on the basis of DC measurements. The noise is negligible for degradation when the wiring inductance is smaller than 250 m Omega . In terms of device structure dependence, for SD and LDD, enhanced AC degradation was observed during channel hot-electron (CHE) stress. No acceleration occurred with drain avalanche hot-carrier (DAHC). In LDD, this enhancement can be attributed to stronger DAHC stress during gate pulse transients, while in SD, trapping of channel hot electrons at neutral traps created at the rising and the falling edges of gate pulses acted as an additional acceleration factor. In the case of GOLD, however, no difference between AC and DC stress was seen for DAHC or CHE conditions, and CHE stress was more severe than DAHC stress, which was possibly due to a large gate current characteristic.<<ETX>>

0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation

A 0.3-/spl mu/m mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si/sub 3/N/sub 4/ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm. >

Self diffusion of Li+-ions in LixTi1+yS2 (v = 0.01–0.11)

Abstract Self diffusion of Li + ions in Li x Ti 1+y S 2 ( x =0–1, y =0.01–0.11) has been studies by means of the 7 Li NMR relaxation time T 1ϱ . Li x Ti 1.01 S 2 , with an approximately stoichiometric Ti content, had a self diffusion coefficient of 2 × 10 −10 cm 2 s −1 at 25°C for x ≤ 0.8. On the other hand, samples with the composition deviated from the stoichiometry had lower self diffusion coefficients and higher activation energies. Excess Ti ions showed the pinning and blocking effects which inhibit the Li + -ion diffusion in the interlayer of TiS 2 .

Metallized ultra-shallow-junction device technology for sub-0.1 /spl mu/m gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 /spl mu/m MOSFETs. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability. >

High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W

This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.

Stress‐induced rearrangement of oxygen atoms in Si investigated by a monoenergetic positron beam

A monoenergetic positron beam has been used to investigate the state of interstitial oxygen in Czochralski‐grown Si with coverage of SiO2 (100 nm) and poly‐Si (200 nm)/SiO2 (100 nm), respectively. It was found that (i) the growth of SiO2 gives rise to a strong Doppler broadening of positrons in the bulk of Si and (ii) such a broadening can be recovered to the original level by annealing at 450 °C, by the removal of overlayers using chemical etching and by long‐term aging at room temperature. This broadening was assigned to arise from the positron trapping by oxygen interstitial clusters. It was concluded that film stress is responsible for the rearrangement of oxygen atoms in Czochralski‐grown Si.

Formation of oxygen-related defects enhanced by fluorine in BF2+-implanted Si studied by a monoenergetic positron beam

Defects in 25-keV BF2+- or As+-implanted Si specimens were probed by a monoenergetic positron beam. For the As+-implanted specimen, the depth profile of defects was obtained from measurements of Doppler broadening profiles as a function of incident positron energy. The major species of the defects was identified as divacancies. For ion-implanted specimens after annealing treatment, oxygen-related defects were found to be formed. For the BF2+-implanted specimen before annealing treatment, such defects were formed in the subsurface region, where oxygen atoms were implanted by recoil from oxide films. This was attributed to enhanced formation of oxygen-related defects by the presence of F atoms.

Low-Voltage High-Gain 0.2 μm N-Channel Metal Oxide Semiconductor Field Effect Transistors by Channel Counter Doping with Arsenic

A counter-doped n-channel metal oxide semiconductor field effect transistor (NMOSFET) whose threshold voltage is controlled by channel counter doping with arsenic is proposed in order to realize a sub-half-micron device with low threshold voltage. It is found that threshold voltage adjustment is possible without losing good short-channel characteristics. The counter-doped NMOSEET is applicable to 0.2 µm devices with a threshold voltage of 0.2 V. Electron mobility of this transistor is found to be 30% higher than that of conventional devices. Smaller gate current also reduces hot carrier-induced threshold voltage shift.

Pseudo-SOI: p-n-p channel-doped bulk MOSFET for low-voltage high-speed applications

A pseudo-silicon-on-insulator (P-SOI) MOSFET fabricated using a bulk substrate has been developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFET, without problems caused by the usage of an SOI substrate. It features a p-n-p channel profile, in which a sandwiched thin n-type layer is fully depleted by the internal built-in potential. The thin n-type layer expands the depletion layer in the inversion state and reduces the vertical electric field at the MOS interface. As a result, the P-SOI MOSFET has a high drain-current drivability, a small subthreshold swing, and a low substrate-bias coefficient. A TiN gate electrode, which has a near midgap work function, is used to achieve optimum threshold voltage. It also increases the drain current by reducing the gate-electrode depletion. Counter doping to the buried p-type layer below the source and drain reduces junction capacitances. The subthreshold swing of the fabricated 0.25-/spl mu/m-gate-length P-SOI MOSFET becomes 73 mV/decade. Its drain current is 25% higher, substrate-bias coefficient is 40% lower, and source/drain junction capacitance is 60% lower, than those of a control MOSFET.

A NEW FIELD-EFFECT TRANSISTOR BASED ON THE METAL-INSULATOR TRANSITION

We propose a field‐effect tunnel transistor based on the metal–insulator transition. The principle of the switching is the metal–insulator transition, which occurs at the sheet resistance RQ (∼h/e2=25.8 kΩ). The modulation of the sheet resistance around RQ by the control gates can be magnified by the phase transition. As a result, high transconductance and high current drivability more than 10 times greater than the ultimate silicon metal‐oxide‐semiconductor transistors are obtained. The device is a thin‐film silicon‐on‐insulator structure with dual gates, one on each side of the channel. A very thin granular metal film is deposited on the Si layer. Each metal island forms a Schottky contact with the Si layer, which is completely depleted. The electrons in the metal tunnel between the islands through the Si. The metal film can have a higher Coulomb gap and current drivability than is obtained with a single tunnel junction. A temperature of less than 1/20 of the Coulomb gap energy is required to reduce the...